Board Component Blocks - Altera Cyclone V GT FPGA Reference Manual

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Board Component Blocks

The development board features the following major component blocks:
■ One Cyclone V GT FPGA (5CGTFD9E5F35C7N) in a 1152-pin FineLine BGA
(FBGA) package
■ FPGA configuration circuitry
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■ Clocking circuitry
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Memory
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Communication Ports
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Cyclone V GT FPGA Development Board
Reference Manual
®
MAX V CPLD (5M2210ZF256C4N) in a 256-pin FBGA package as the System
Controller
MAX II CPLD (EPM570GT100C3N) in a 100-pin FBGA package as part of the
TM
embedded USB-Blaster
MAX II CPLD (EPM570ZM100) in a 100-pin MBGA package for use with ASSP
(optional)
Flash fast passive parallel (FPP) configuration
Si570 and Si571 programmable oscillators
50-MHz, 100-MHz, and 125-MHz oscillators
DDR3 SDRAM
DDR3A provides 256 Mbyte (MB) with ECC using three devices, each
■
having a 16-bit interface to a hard memory controller
DDR3B provides 512 MB using four devices, each having a 16-bit interface
■
to a soft memory controller
One 1-gigabit (Gb) synchronous flash with a 16-bit data bus
One PCI Express x4 Gen1 socket
Two universal HSMC ports
One Gigabit Ethernet port
One serial digital interface (SDI) port (optional)
One SMA clock or data output
II for use with the Quartus
Chapter 1: Overview
Board Component Blocks
®
II Programmer
August 2017 Altera Corporation