Altera Cyclone V GT FPGA Reference Manual page 41

Chapter 2: Board Components
Components and Interfaces
Table 2–22. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6)
Board
Schematic Signal Name
Reference
18
HSMB_RX_P3
19
HSMB_TX_N3
20
HSMB_RX_N3
21
HSMB_TX_P2
22
HSMB_RX_P2
23
HSMB_TX_N2
24
HSMB_RX_N2
25
HSMB_TX_P1
26
HSMB_RX_P1
27
HSMB_TX_N1
28
HSMB_RX_N1
29
HSMB_TX_P0
30
HSMB_RX_P0
31
HSMB_TX_N0
32
HSMB_RX_N0
33
HSMB_SDA
34
HSMB_SCL
35
JTAG_TCK
36
HSMB_JTAG_TMS
37
HSMB_JTAG_TDO
38
HSMB_JTAG_TDI
39
HSMB_CLK_OUT0
40
HSMB_CLK_IN0
41
HSMB_WEn
42
HSMB_RASn
43
HSMB_ADDR_CMD0
44
HSMB_CASn
47
HSMB_DQ0
49
HSMB_DQ1
53
HSMB_DQ2
55
HSMB_DQ3
59
HSMB_DQ4
61
HSMB_DQ5
65
HSMB_DQ6
67
HSMB_DQ7
71
HSMB_DQ8
73
HSMB_DQ9
77
HSMB_DQ10
79
HSMB_DQ11
August 2017 Altera Corporation
Cyclone V GT
I/O Standard
Pin Number
G2 1.5-V PCML
F3 1.5-V PCML
G1 1.5-V PCML
H4 1.5-V PCML
J2 1.5-V PCML
H3 1.5-V PCML
J1 1.5-V PCML
K4 1.5-V PCML
L2 1.5-V PCML
K3 1.5-V PCML
L1 1.5-V PCML
M4 1.5-V PCML
N2 1.5-V PCML
M3 1.5-V PCML
N1 1.5-V PCML
L20 2.5-V CMOS
E27 2.5-V CMOS
AK5 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
— 2.5-V CMOS
D25 2.5-V CMOS
A22 2.5-V CMOS
B24 2.5-V CMOS
A23 2.5-V CMOS
L18 2.5-V CMOS
C21 2.5-V CMOS
E22 2.5-V CMOS
G20 2.5-V CMOS
F20 2.5-V CMOS
D24 2.5-V CMOS
C26 2.5-V CMOS
G21 2.5-V CMOS
F21 2.5-V CMOS
D27 2.5-V CMOS
F23 2.5-V CMOS
C29 2.5-V CMOS
E24 2.5-V CMOS
H21 2.5-V CMOS
Description
Transceiver RX bit 3
Transceiver TX bit 3n
Transceiver RX bit 3n
Transceiver TX bit 2
Transceiver RX bit 2
Transceiver TX bit 2n
Transceiver RX bit 2n
Transceiver TX bit 1
Transceiver RX bit 1
Transceiver TX bit 1n
Transceiver RX bit 1n
Transceiver TX bit 0
Transceiver RX bit 0
Transceiver TX bit 0n
Transceiver RX bit 0n
Management serial data
Management serial clock
JTAG clock signal
JTAG mode select signal
JTAG data output
JTAG data input
Dedicated CMOS clock out
Dedicated CMOS clock in
Write enable
Row address select
Memory address or command
Column address select
Memory data bus
Memory data bus
Memory data bus
Memory data bus
Memory data bus
Memory data bus
Memory data bus
Memory data bus
Memory data bus
Memory data bus
Memory data bus
Memory data bus
Cyclone V GT FPGA Development Board
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Reference Manual