Analog Devices ADSP-21375 Manual page 30

External Memory
Table 1-1 provides start and end addresses of the board's external
memories.
Table 1-1. EZ-KIT Lite Evaluation Board External Memory
Start Address End Address
0x0020 0000 0x011F 0000
0x0400 0000 0x040F FFFF
0x0800 0000 0x08FF FFFF
0x0800 0000 0x0BFF FFFF
0x0C00 0000 0x0CFF FFFF
0x0C00 0000 0x0FFF FFFF
The parallel flash memory and SDRAM connect to the external memory
of the processor.
The SDRAM memory connects to the SDRAM controller of the proces-
sor. A set of programmable timing parameters is available to configure the
SDRAM banks to support slower memory accesses. Care must be taken
when configuring the SDRAM control registers. For more information
regarding the setup of the SDRAM controller, please refer to the
ADSP-21368 SHARC Processor Hardware Reference (includes
ADSP-21375). An example program is included in the EZ-KIT Lite
installation directory to demonstrate the SDRAM setup.
The SPI flash memory connects to the SPI port of the processor and
designates:
• DPI pin 5 (
• DPI pin 3 (
• DPI pin 1 (
• DPI pin 2 (
1-8
Content
SDRAM memory (
Flash memory (
Unused chip select (
Unused chip select (
Unused chip select (
Unused chip select (
) as a chip select
DPI5
) as the SPI clock
DPI3
) as the
DPI1 MOSI
) as the
DPI2 MISO
ADSP-21375 EZ-KIT Lite Evaluation System Manual
)
~MS0
)
~MS1
) for non-SDRAM addresses
~MS2
) for SDRAM address
~MS2
) for non-SDRAM addresses
~MS3
) for SDRAM addresses
~MS3