Jtag Emulation Port - Analog Devices ADSP-21375 Manual

System Architecture
Limits to the current and to the interface speed must be taken into consid-
eration when using the expansion interface. The maximum current limit is
dependent on the capabilities of the used regulator. Additional circuitry
also can add extra loading to signals, decreasing their maximum effective
speed.
Analog Devices does not support and is not responsible for the
effects of additional circuitry.

JTAG Emulation Port

The JTAG emulation port allows an emulator to access the internal and
external memory of the processor through a 6-pin interface. The JTAG
emulation port of the processor also connects to the USB debugging inter-
face. When an emulator connects to the board at
interface is disabled. This is not a standard connection of the JTAG
interface.
For information about the standard connection of the interface, see EE-68
published on the Analog Devices Web site. For more information about
the JTAG connector, see
more about available SHARC processor emulators, go to
http://www.analog.com/processors/sharc/evaluationDevelop-
ment/crosscore/index.html
2-8
"JTAG Header (ZP4)" on page
.
ADSP-21375 EZ-KIT Lite Evaluation System Manual
, the USB debugging
ZP4
2-25. To learn