External Pll; Expansion Interface - Analog Devices ADSP-21375 Manual

The signals are available externally via the expansion interface con-
FLAG
nectors ( ). The pinout of these connectors can be found in
J1–3
"ADSP-21375 EZ-KIT Lite Schematic" on page

External PLL

The ADSP-21375 EZ-KIT Lite contains an external phase lock loop to
help generate a faster and more stable master input clock
uses DAI pin 3 as an input clock from the ADSP-21375 processor. The
new clock generated by PLL connects to the processor via DAI pin 2.
Example programs are included in the EZ-KIT Lite installation directory
to demonstrate how to configure and use the board's external PLL.

Expansion Interface

The expansion interface consists of the three 90-pin connectors.
shows the interfaces each connector provides. For the exact pinout of the
connectors, refer to
The mechanical dimensions of the connectors can be obtained from
nical or Customer
Table 2-2. Expansion Interface Connectors
Connector Interfaces
5V,
J1
3.3V,
J2
5V, 3.3V, reset, parallel port control signals
J3
ADSP-21375 EZ-KIT Lite Evaluation System Manual
ADSP-21375 EZ-KIT Lite Hardware Reference
"ADSP-21375 EZ-KIT Lite Schematic" on page
Support.
,
ADDR23–0 DATA31–0
, ,
FLAG3–0 DAIP20–1 DPI14–1
B-1.
MCLK
, SDRAM control signals
. The PLL
Table 2-2
B-1.
Tech-
2-7