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8/16 Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between PCI-
originated I/O cycles to the ISA bus. This delay takes place
because the PCI bus is so much faster than the ISA bus.
These two fields let you add recovery time (in bus clock cycles) for
16-bit and 8-bit I/O.
The choices: NA, 1-8 (8-bit I/O) ; NA, 1-4 (16-bit I/O).
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. The user informa-
tion of peripherals that need to use this area of system memory
usually discusses their memory requirements.
The choices: Disabled, Enabled.
Passive Release
When "Enabled", CPU to PCI bus accesses are allowed during
passive release. Otherwise, the arbiter only accepts another PCI
master access to local DRAM.
The choices: Disabled, Enabled.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Please select "Enabled" to support
compliance with PCI specification version 2.1.
The choices: Disabled, Enabled.
AGP Aperture Size (MB)
Select the size of the Accelerated Graphics Port (AGP) aperture.
The aperture is a portion of the PCI memory address range dedicat-
ed for graphics memory address space. Host cycles that hit the
aperture range are forwarded to the AGP without any translation.
The choices: 4, 8, 16, 32, 64, 128, 256.
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GENE-6320 User Manual
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