Pci Delay Transaction; Agp Master 1 Ws Write; Agp Master 1 Ws Read - Aaeon PCM-6892 User Manual

PCI Delay Transaction

The chipset has an embedded 32 -bit posted write buffer to support
delay transactions cycles. Select enabled to support compliance
with PCI specification version 2.1.
The choices: Enabled, Disabled.
PCI#2 Access #1 Retry
When disabled, PCI#2 will be connected until access
finishes(default). When enabled, PCI#2 will be disconnected if max
retries are attempted without success.
The choices: Enabled, Disabled.

AGP Master 1 WS Write

System will run single wait state delay before writing data from
buffer. If the setting is configured as disabled, system will run twice
wait states so that system can be more stable.
The choices: Enabled, Disabled.

AGP Master 1 WS Read

System will run single wait state delay before reading data from
buffer. If the setting is configured as disabled, system will run twice
wait states so that system can be more stable.
The choices: Enabled, Disabled.
Chapter 3 Award BIOS Setup 55