Sdram Pins - Xilinx Virtex-II Pro User Manual

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19. SDRAM Pins

The system clock that enables proper communication between the SDRAM and the DUT is
GCLK1P.
types.
Table 1-10: System Clock for SDRAM and DUT
SDRAM Pin
Table 1-11
Table 1-11: SDRAM to FPGA Pin Mapping
SDRAM Pin
22
Table 1-10 shows the system clock pin locations for the available DUT package
FG456
CLK E12
shows the pin mapping from the SDRAM to the available DUT package types.
FG456
DQ0 T2
DQ1 T3
DQ2 T1
DQ3 R1
DQ4 R2
DQ5 N2
DQ6 U2
DQ7 N1
DQ8 Y1
DQ9 M3
DQ10 W2
DQ11 V1
DQ12 V2
DQ13 N4
DQ14 M4
DQ15 N3
DQ16 K4
DQ17 H1
DQ18 K3
DQ19 K1
DQ20 K2
DQ21 J2
DQ22 H3
DQ23 J1
DQ24 F2
DQ25 G1
DQ26 F1
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Chapter 1: Virtex-II Pro Prototype Platform
FF672 FF1152
D14 D18
FF672 FF1152
H3 N8
J4 N9
H4 N10
G4 M6
G3 N4
E3 M4
J3 N7
E4 M7
N4 AB2
K4 W10
N3 AA3
M3 Y6
M4 AA2
L3 Y7
K3 W9
L1 W8
N2 L4
G1 M3
L2 L5
J1 P7
K1 L6
J2 P8
H2 M2
H1 N1
E2 K1
E1 L3
D1 K2
Virtex-II Pro Prototype Platform User Guide
UG027 / PN 0402044 (v1.6) October 25, 2002