Xilinx Virtex-II Pro User Manual page 23

User Programmable Pins
Table 1-11: SDRAM to FPGA Pin Mapping (Continued)
SDRAM Pin
Notes:
1. For proper operation of the SDRAM, use the LVCMOSDCI25 voltage standard on the FPGA pins.
2. CS # is tied to the jumper labeled RAM_ENABLE/RAM_DISABLE.
3. Disable the SDRAM when using the DUT pins as standard I/O pins.
4. The SDRAM is a Samsung K4S64323LF-S(D)G/S75. For information on its operation, see:
Virtex-II Pro Prototype Platform User Guide
UG027 / PN 0402044 (v1.6) October 25, 2002
FG456
DQ27 E1
DQ28 E3
DQ29 D2
DQ30 G2
DQ31 D1
A0 J4
A1 J3
A2 F4
A3 F3
A4 G3
A5 G4
A6 K5
A7 G5
A8 P2
A9 L2
A10 H4
DQM0 P3
DQM1 M2
DQM2 H5
DQM3 E4
RAS# J6
CAS# M5
WE# U3
CKE L3
BA0 K6
BA1 L4
http://www.samsungelectronics.com/semiconductors/DRAM/Mobile_SDRAM/64M_bit/K4S64323
LF/ds_k4s64323lf-s(d)g_s.pdf
www.xilinx.com
1-800-255-7778
FF672 FF1152
C2 K4
C1 L7
B1 K5
F1 L1
A2 F5
R3 N3
T3 N2
P3 P2
V3 AA4
W2 AB3
Y3 W5
U1 AA1
W3 Y9
U3 AA6
T2 Y3
R2 R3
V4 W6
W1 AC1
P4 L8
V1 AA5
W4 W11
T4 R9
U4 W7
T1 Y1
R4 R10
P2 V11
R
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