Motorola MC68824 User Manual page 95

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bus arbitration cycles, and it is monitored to determine when the TBC can take control of the bus
(after the TBC has requested and been granted use of the bus).
5.3.7 Chip Select (CS)
This input pin is used by the TBC to determine when it has been selected by the host processor.
When CS is asserted, the address on A 1, A2, and the data strobes select the internal TBC register
that will be involved in the transfer. CS should be generated by qualifying an address decode
signal with the address and data strobes. Asserting CS when the TBC is bus master will cause
an address error to occur.
5.4 BUS ARBITRATION
The signals in this group form a bus arbitration circuit that determines which device is the current
bus master.
5.4.1 Bus Request (BR)
This open-drain ouptut pin is wire-ORed with all other devices that could be bus masters and is
asserted to request control of the bus.
5.4.2 Bus Grant (BG)
BG is an input that indicates to the TBC that bus control has been granted and that it may assume
bus mastership as soon as the current bus cycle is completed. The TBC will not take control of
the bus until AS and BGACK are negated and the BEC pins are encoded as normal mode.
5.4.3 Bus Grant Acknowledge (BGACK)
BGACK is a bidirectional three-state signal. When BGACK is an asserted input signal to the TBC,
it indicates that some other device has become the bus master. This signal will not be asserted
as an output to indicate that the TBC is the current bus master until the following conditions are
met:
1. Bus request (BR) is asserted.
2. A bus grant (BG) has been received.
3. Address strobe (AS) is inactive, indicating that the current bus cycle has ended.
4. Bus grant acknowledge (BGACK) is inactive, which indicates that no other device is still
claiming bus mastership.
5. BEC pins are encoded as normal mode.
5.5 INTERRUPT CONTROL
Two signals are used to perform the request/acknowledge handshake function between the TBC
and the host processor.
MOTOROLA
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MC68824 USER'S MANUAL