Motorola MC68824 User Manual page 37

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TP - Token Passed
This bit is set when the TBC believes it has successfully passed the token to its successor
station. When this event occurs, the TBC stores the token rotation time (TRT) value into the
last token_rotation_time and begins a new TRT measurement.
BAERR - Bus/Address Error
This bit is set when a bus or address error occurs in a TBC DMA cycle. Bus error is indicated
on the BEC pins, while an address error is generated when the TBC is bus master and CS or
lACK is asserted, indicating that the TBC has attempted to address itself.
If a bus or address error occurs, the TBC stops transmitting and receiving data frames. If the
TBC has the token at this time, the TBC will pass the token to its successor. If the TBC does
not have a successor, then it will try to find a new successor. Next, the TBC will dump all
four DMA pointers and their function codes into the dump area in the initialization table
(offset EO through F4) and execute the interrupt routine if the corresponding bit is set in the
interrupt mask word. Note that the pointer which caused the bus/address error may have
been incremented by one or two before its value was dumped. If a bus error occurs during
reception, both free pools are disrupted and must be reinitialized via SET TWO WORDS
commands as part of the bus error handling routine.
The host can cause the TBC to resume full operation by issuing a CLEAR INTERRUPT STATUS
command to clear the bus/address error bit. This command should be given only after the
steps described below have been followed:
• The host has dealt with the cause of the bus/address error.
• The host has given the TBC new pools of free FDs and free BDs.
• The host has enabled the TBC to resume transmitting by issuing the START or RESTART
command if the TBC has more to transmit.
If a second bus/address error occurs before the host has dealt with the first one, (i.e., the
appropriate CLEAR INTERRUPT STATUS command was not given), then the TBC enters an
endless loop of severe interrupts and waits for RESET. If the TBC was in the OFFLINE state
when the first bus/address error occurred, it will immediately enter the severe interrupt state.
FDPL - Frame Descriptor Pool Low
This bit is set when the TBC accesses an FD in the free FD pool whose W_FD (warning frame
descriptor pool low) bit is set. The W_FD bit is intended to be a warning that the FD pool is
running low and that more FDs should be added soon. The host decides in which FD to set
the W_FD bit.
BDPL - BD Pool Low
This bit is set when the TBC accesses a BD in the free BD pool whose W_BD (warning buffer
descriptor pool low) bit is set. The W_BD bit is intended to be a warning that the BD pool is
running low and that more BDs should be added soon. The host decides in which BD to set
the W_BD bit.
OVER - Overrun
This bit when set indicates that the TBC attempted to write to a full FIFO while receiving.
This means that the TBC was not able to empty the FIFO fast enough. If this occurs frequently,
it may indicate that the TBC is not receiving sufficient host bus bandwidth.
UNR - Underrun
If the TBC transmit machine attempts to read from an empty FIFO this bit will be set and an
abort sequence will be sent by the TBC. This indicates that the TBC was not able to fill the
FIFO fast enough. If this occurs frequently, it may indicate that the TBC is not receiving
sufficient host bus bandwidth.
MOTOROLA
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MC68824 USER'S MANUAL