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Motorola MC68360 User Manual

Asynchronous hdlc, async hdlc protocol microcode.
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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR
TECHNICAL INFORMATION
Asynchronous HDLC
MC68360 ASYNC HDLC Protocol Microcode
User's Manual
Rev 1.1
January 24, 1996
For More Information On This Product,
Go to: www.freescale.com

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Table of Contents

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   Summary of Contents for Motorola MC68360

  • Page 1 Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL INFORMATION Asynchronous HDLC MC68360 ASYNC HDLC Protocol Microcode User’s Manual Rev 1.1 January 24, 1996 For More Information On This Product, Go to: www.freescale.com...
  • Page 2: Table Of Contents

    Freescale Semiconductor, Inc. Asynchronous HDLC Asynchronous HDLC ASYNC HDLC Controller Overview ASYNC HDLC Controller Key Features ASYNC HDLC Channel Frame Transmission Processing ASYNC HDLC Channel Frame Reception Processing Transmitter Transparency Encoding Receiver Transparency Decoding 2.4.1 Receive Flowchart 2.4.2 Cases not covered by RFC 1549 Implementation Specifics related to Asynchronous HDLC 2.5.1 FLAG sequence...
  • Page 3 Freescale Semiconductor, Inc. Asynchronous HDLC Differences Between HDLC and ASYNC-HDLC Max Received Frame Length Counter Frame termination due to error Commands Automatic Error Counters Noisy Characters Appendix A - Microcode Initialization Procedure Initialization Procedure for QUICC Version $0001 Initialization Procedure for QUICC Revision $0002 Initialization Procedure for QUICC Version $0003 Appendix B - Programming Example Appendix C - References...
  • Page 4: Asynchronous Hdlc

    The ASYNC HDLC controller will then proceed to the next Tx BD in the table. If it is not ready, the ASYNC HDLC controller will wait until the Tx BD is ready. MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 5: Async Hdlc Channel Frame Reception Processing

    • The byte is a FLAG (0x7E) • The byte is a Control-Escape Character (0x7D) MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 6: Receiver Transparency Decoding

    For more information on the transparency algorithm, please see the references in Appendix C - References. The receive Flow-chart is shown below to detail the algorithm because there are some cas- es which are not addressed in the RFC. MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 7: Receive Flowchart

    “modified” by the xor process. It is assumed that this will be caught by the CRC check. • In addition to the Abort sequence, frames will be terminated by following errors: —Noisy Character received MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 8: Implementation Specifics Related To Asynchronous Hdlc

    When transmitting, the Asynchronous HDLC controller will transmit IDLE characters (char- acters consisting of only “1”s) when no data is available for transmission. When receiving, the Asynchronous HDLC controller will ignore any IDLE characters. MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 9: Microcode Use

    QUICC using the ASYNC-HDLC micro- code. This table can be used in conjunction with the table in Appendix A of the MC68360 User’s Manual to determine if your desired configuration can be handled by the QUICC.
  • Page 10 If the bit is not set, the character corresponding to that bit will be received normally. 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 ....0x05 0x04 0x03 0x02 0x01 0x00 MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 11: Configuring The General Scc Parameters

    The receive errors are reported through the Rx BD. The transmit errors are reported through the Tx BD. An indication about the status lines (CD and CTS) is reported through the port C MOTOROLA For More Information On This Product,...
  • Page 12: Async Hdlc Command Set

    5.1 ASYNC HDLC Command Set The following commands are issued to the Command Register (CR) documented in Section 7.1 of the MC68360 User’s Manual. 5.1.1 Transmit Commands After a hardware or software reset and the enabling of the channel in the SCC mode regis- ter, the channel is in the transmit enable mode and starts polling the first BD in the table ev- ery 8 transmit bit-times, or immediately if the TOD bit in the TODR is set.
  • Page 13: Receive Commands

    When this error occurs, the channel terminates frame reception, closes the buffer, sets the Carrier Detect lost (CD) bit in the BD, and sets the RXF bit in the event register. This error MOTOROLA For More Information On This Product,...
  • Page 14: Registers

    A bit is cleared by writing a one (writing a zero does not affect a bit’s value). More than one bit may be cleared at a time. All unmasked bits must be cleared before the CP will clear the internal interrupt request. This register is cleared at reset. MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 15: Async Hdlc Mode Register (psmr)

    0— Normal Operation. 1— Asynchronous flow control. When the CTS pin is negated, the transmitter will stop transmitting at the end of the current character. (If CTS is negated past the middle MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 16: Async-hdlc Rx Buffer Descriptor

    RXF operation remains unaffected. 1— The RXB or RXF bit in the ASYNC HDLC Event Register will be set when this buff- er has been used by the ASYNC HDLC controller. MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 17 (including the 2 bytes for CRC). Note If the received frame has a length (plus CRC) which is an exact multiple of MRBLR, the BD with the “L” bit set will not actually MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 18: Async-hdlc Tx Buffer Descriptor

    0— The TXB bit in the ASYNC HDLC Event Register will not be set after this buffer has been used. 1— The TXB bit in the ASYNC HDLC Event Register will be set when this buffer has been transmitted by the ASYNC HDLC controller. MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 19: Differences Between Hdlc And Async-hdlc

    For example, if a CD lost error occurred, the frame will be closed and the par- MOTOROLA For More Information On This Product,...
  • Page 20: Commands

    9.5 Noisy Characters Noisy characters (those whose three samples are not the same) are not accounted for in this controller. It is assumed that the CRC will catch any data integrity problems. MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 21: Appendix A - Microcode Initialization Procedure

    6. Write $0001 to the RCCR register 7. Write $8000 to the CR register Note If the QUICC is ever reset (by RESETS or RESETH), the micro- code must be reloaded and reinitialized. MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 22: Initialization Procedure For Quicc Version $0003

    6. Write $0001 to the RCCR register 7. Write $8000 to the CR register Note If the QUICC is ever reset (by RESETS or RESETH), the micro- code must be reloaded and reinitialized. MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 23: Appendix B - Programming Example

    19. Program the GSMR_L register to ASYNC HDLC mode, but do not turn on the trans- mitter or receiver. 20. Set the PSMR register appropriately. (see Section 6.2) 21. Turn on the transmitter and receiver in the GSMR_L register. MOTOROLA For More Information On This Product, Go to: www.freescale.com...
  • Page 24: Appendix C - References

    [1] “RFC 1549 - PPP in HDLC Framing”, W. Simpson, December 1993. [2] “RFC 1548 - The Point-to-Point Protocol (PPP)”, W. Simpson, December 1993. These two documents can be obtained via anonymous FTP from nic.ddn.mil in the /rfc di- rectory. MOTOROLA For More Information On This Product, Go to: www.freescale.com...

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