Table of Contents
Advertisement
II
should be at least 64 bytes in this mode. Note that the lower bridge mode (bit 4) and the
recognize source routing mode are mutually exclusive. If both modes are set, recognize source
routing mode takes precedence. See
APPENDIX C BRIDGING
for details.
3.3.3 SET MODE 3
Command
The default setting is zero for all modes described in this subsection except for the halt generator
enable mode (HLEN) whose default is one. This command is normally given only as part of an
initialization sequence or during testing.
7 6 5 4 3 2 1
o
I
1
I
1
I
RCDS
I
TCDS
IHLEN I
SWAP
I
PS3
RCDS - RX CRC to Data Storage Mode
1 Copy RX CRC as part of the data unit
o
Do not copy RX CRC as part of the data unit.
This mode causes the TBC to copy the 4-byte CRC of data frames to memory as part of the
data unit. The CRC is counted in the reported data unit length. Regardless of this mode, the
CRC is checked for correctness and, if erroneous, the TBC will not accept the frame unless
so specified in·the RX frame status error mask in the private area (offset 26).
TCDS - TX CRC Disable Mode
1 CRC not generated by the TBC for data frames
o
CRC generated by the TBC
This mode disables CRC generation on data frames transmitted by the TBC. In this case, the
user must supply a correct CRC at the end of the data unit. According to the 802.4 standard,
all frames are transmitted with the standard 32-bit frame check sequence (FCS) and the FCS
or CRCis checked for correctness in all received frames. Received frames with CRC errors are
treated as noise bursts by the access control machine (ACM). This mode applies to all data
frames, i.e., there is not a separate indication for each frame. The TBC always generates and
attaches the CRC for all control frames, even when this mode is on. This mode can be used
for testing or for use with a non-standard, user specified CRC.
NOTE
In the latter case, receiving stations may identify data frames as noise bursts.
The CRC error bit in the RX status error mask located in the private area must
be set in order to accept such frames.
HLEN - Halt Generator Enable Mode
1 Halt generator enabled
o
Halt generator not enabled
This mode controls the maximum number of DMA transfers that the TBC performs in one
DMA burst. If the user wishes to give the maximum memory bandwidth to the TBC, HLEN
should be set to zero. This will allow the TBC to, for example, empty or fill the FIFO in one
burst. If the user wishes to limit TBC DMA bursts, HLEN should be set to one. This will cause
the TBC to release the bus after a maximum of eight memory cycles. In this case, if the FIFO
is not empty or full, the TBC will request the bus again. After RESET, HLEN is enabled.
SWAP - Data Byte Swap Mode
1 Data in memory buffers organized with high order byte in higher address (Digital and
Intel convention)
MOTOROLA
3-10
MC68824 USER'S MANUAL
Advertisement
Chapters
Table of Contents
