Bus Arbitration Unit State Diagram - Motorola MC68824 User Manual

~
ANY STATE
I
I
NRM & REO
IDLE WAITS FOR
NRM TO REQUEST
NRM
NRM & BGF
BUS REOUEST
WAITS FOR NRM
TO OWN BUS
NRM
NRM & BGF
(HALT & DTACK & REOII RRT
RESET - RESET
NRM - NORMAL (NO EXCEPTIONI
REO - INTERNAL TRANSFER REOUEST
HALT - HALT
DTACK - DTACK ACTIVE
BERR - BUS ERROR
BGF - BUS GRANTED AND FREE
RTY - RETRY
RRT - RELINQUISH AND RETRY
UNO - UNDEFINED EXCEPTION
RESET
IDLE
!
REO &
NRM
BUS REOUEST
WAITS FOR BGF
TO OWN BUS
NRM &
BGF
BERRI (REQ &
KII
KII
Kill
((NRM & DTAC
(UNO & DTAC
(HALT & DTAC
MASTER
ACTIVE
NRM
f
l
RTYI (DT ACK &
NOI
REQ & U
MASTER
WAITS FOR NRM
Figure 6-13. Bus Arbitration Unit State Diagram
6.5 BUS OVERHEAD TIME
In asynchronous bus systems, such as those defined for the M68000 Family, a certain amount of
time is used to synchronize incoming signals. This is "wasted time" since no data transfer activity
can take place during those periods. In many applications, the synchronization overhead time
required to switch bus masters must be known to predict system behavior.
For the TBC, there are two types of overhead:
Time for the TBC to take control of the bus (front-end overhead), and
Time that occurs when the TBC releases control of the bus to another bus master (back-end
overhead).
The timing diagram for the front-end and back-end overhead for the TBC is shown in Figure 6-
14.
6.5.1 Front-End Overhead
This overhead is the delay that occurs from the time that the host processor terminates a bus
cycle by negating AS to when the TBC starts the bus cycle by placing the function codes and
address information on the bus. It is assumed that BG is asserted and BGACK is negated prior
to negation of AS by the host processor so that no additional synchronization delays are introduced'
by those signals. After one synchronization delay plus one and a half clock cycles, the TBC asserts
BGACK to assume control of the bus and begin the DMA cycle. The front-end overhead is between
two-and-a-half and three-and-a-half clock cycles.
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