Interrupt Acknowledge Cycle - Motorola MC68824 User Manual

The interrupt acknowledge operation is started by the TBC when interrupt acknowledge (lACK)
and lower data strobe (LOS) are asserted by the host processor. The TBC responds by placing its
interrupt vector number on 00-07 and asserting data transfer acknowledge (DTACK). During this
operation, A1-A31 and UDS/AO are ignored by the TBC. The vector number remains on the data
bus until lACK or LOS is negated by the host processor. When this occurs, the TBC will three state
the data lines and then negate and three state DTACK. The timing for this operation is shown in
Figure 6-3.
50 51 52 53 54 55 5W 5W 56 57 50
CLK
(INPUT)
L05 ,
(INPUT) _ _ ----'
\~------------~I
lACK ---------------------------------\
(INPUT) '-_ _ _ _ _ _ _ _
----1'
00·07 ( )
(OUTPUT)
-------------------------------------------------< '-_________________________
---J>------
O~CK
__________________________________________
1
(OUTPUT)
\~
_________
~f'--------
R/W ----------------------,..,......------------------------------------------------------------------------------
(IN PUT) _________________ ---'
Figure 6-3. Interrupt Acknowledge Cycle
6.2 DMA OPERATION
In the DMA operation mode or master mode, the TBC is the bus master and performs memory
read and write operations. The TBC can operate in either an a-bit or a 16-bit bus configuration.
NOTE
The TBC does not check for an "odd pointer" and does not generate an address error
for an odd word boundary. For an a-bit data bus, an "odd pointer" is proper. For a 16-
bit bus, the TBC zeros the least significant address bit and therefore always presents an
even word address to the bus. The system designer must ensure that the TBC is not
supplied with an "odd pointer" in a 16-bit configuration.
6.2.1 DMA Burst Control
The TBC has an operation mode that controls the maximum number of DMA transfers that the
TBC can perform in one DMA burst. The operation mode bit is called halt generator enable (HLEN)
and is controlled by the SET MODE 3 command. If the TBC is to be
giv~n
the maximum memory
bandwidth, HLEN should be set to zero. In this case the TBC will empty or fill the FIFO in one
DMA burst. If the TBC is to have limited DMA burst, HLEN should be set to one. In this case, the
TBC will release the bus after a maximum of eight memory cycles. If the FIFO is not empty or
full, the TBC will request the bus again. This limited DMA burst mode provides an upper bound
for latency and allows other masters to access the memory.
MC68824 USER'S MANUAL
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