Tbc Read Cycle With Relinquish And Retry, Early And Late - Motorola MC68824 User Manual

6.3.5 Relinquish and Retry
If the BEC pins are encoded with a logical four, then the TBC terminates the current bus cycle
and relinquishes bus mastership. One debounce delay after the BEC pins have returned to normal,
the TBC rearbitrates for the bus and reruns the same bus cycle as shown in Figure 6-10.
6.3.6 Reset
ClK
(INPUT!
Al·A31
(OUTPUT!
AS.
UOS. lOS
(OUTPUT!
00·015
(INPUT!
OTACK
(INPUT!
ART ON
BECO·BEC2
(INPUT!
OTACK
(INPUT!
ART ON
BECO·BEC2
(INPUT!
BGACK
(OUTPUT!
Bii
(OUTPUll
SO SI S2 S3 S4 S5 S6 S7
sa
S9 SlO Sl1
=x
,
______________
-J>~----------­
~--------~;-'--------------
-----------~( >~---------
'---_---'/~----
}
~R"
\
\
/ } lATE
,'--__ -J/
----------------------------/
Figure 6-10. TBC Read Cycle with Relinquish and Retry, Early and Late
A logical seven encoded on the BEC pins causes the TBC to execute an internal reset sequence.
Hardware and software reset will cause the TBC to execute the same steps, see 3.2.5 RESET
Command for more details.
6.3.7 Undefined BEC Codes
If a logical five or six is encoded on the BEC pins, the TBC takes no action as shown in Figure 6-
11. However, the bus cycle may be extended one more clock cycle due to the debouncing of BEC
lines. The TBC terminates the current cycle after DTACK is asserted.
6.4 BUS ARBITRATION
Bus arbitration is a technique used by bus master devices to request, be granted, and acknowledge
bus mastership. In its simplest form, it consists of the following .
• Asserting a bus mastership request.
• Receiving a bus grant indicating that the bus is available at the end of the current cycle.
MOTOROLA
6-8
MC68824 USER'S MANUAL