Motorola MC68824 User Manual page 122

8.5 AC ELECTRICAL CHARACTERISTICS (Concluded)
NOTE5:
1. If OTACK satisfies the asynchronous setup time (1), then (48) is required for the data-in setup time and (58) for the synchronous
exception setup time. Erroneous behavior may occur if (58) is not satisfied.
2. If OTACK does not satisfy (1
I,
then (49) is required for data-in and (57) for the exception. Erroneous behaviour may occur if (57)
is not satisfied.
3. Active exception when OTACK is absent must satisfy the asynchronous setup time (59).
4. RiW rises on the end of a write cycle (Le., on the...,phase following 57). If the TBC relinquishes the bus, then RiW is three-stated
one phase later. When the TBC takes the bus, RIW is three-stated until 51 and rises on that phase.
5. Data (3) and OTACK (7) will be timed from the earliest clock on which C5 and either data strobe are recognized during an MPU
cycle. Data (3) and OTACK will be timed from the earliest clock on which lACK and either data strobe during an lACK cycle.
6. If CS or lACK is negated before UOS/LDS, the data bus will be three-stated (4),
pos~
before UOS/LD5 negation.
7. If an 8-bit bus is used only LOS need be considered. If a 16-bit bus is used, both UOS and LOS must negate to apply to this
specification.
8. The clock signal used during test has 5 ns of rise time and 5 ns of fall time. For system implementations that have less clock
rise and fall time, the clock pulse minimum should be commensurately wider such that:
1. System (TCL+ (TCR +
TCF)+2)~(minimum
TCYC)+2
2. System (TCH + (TCR + TCF) +
2)~(minimum
TCYC) + 2
CLK
(INPUTI
UOS. LOS
(INPUTI
cs
(INPUT!
00·015
(OUTPUTI
oTACK
(OUTPUTI
R/W
(INPUTI
MC68824 USER'S MANUAL
SO SI S2 S3 S4 S5 SW SW SW SW S6 S7
Figure 8-1. Host Processor Read Cycle
MOTOROLA
II