Write Cycle And Slow Write Cycle; Bec Encoding Definitions - Motorola MC68824 User Manual

Token-passing bus controller
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SO SI S2 S3 S4 S5 S6 S7 SO SI S2 S3 S4 S5 SW SW SW SW SW SW SW SW S6 S7
CLK
(INPUTl
Al·A31
=x
x
(OUTPUTl
-------------------------->--
FCO·FC3
=x
x
(OUTPUTl
-------------------------->--
AS
I
\
1 \
(OUTPUTl
~
________________
~f'__
UOS. LOS
/
\
/
\
(OUTPUTl
______________
~f'__
R/W
--F\
1 \
(OUTPUTl
00·015
<
)
<
(OUTPUTl
------------------~>--
OTACK
\
/
(INPUTl
\
I
Figure 6·5. Write Cycle and Slow Write Cycle
Code
BEC2
BEC1
BECO
Definition
TBC Action
0
H
H
H
NO EXCEPTION
NO AFFECT
1
H
H
L
HALT
HALT AFTER DTACK AND RELEASE THE BUS
(RELEASE BUSI
2
H
L
H
BUS ERROR
TERMINATE THE CURRENT CYCLE AND RELEASE THE BUS
3
H
L
L
RETRY
TERMINATE THE CURRENT CYCLE AND RERUN THE SAME CYCLE AGAIN
AFTER THE EXCEPTION DISAPPEARS
4
L
H
H
RELINQUISH AND
TERMINATE THE CURRENT CYCLE, RELEASE THE BUS, RERUN LAST
RETRY
CYCLE AFTER REARBITRATION
5
L
H
L
UNDEFINED
ONE CLOCK DELAY BEFORE TERMINATION NO FURTHER CYCLES UNTIL
NO EXCEPTION (RESERVEDI
6
L
L
H
UNDEFINED
ONE CLOCK DELAY BEFORE TERMINATION NO FURTHER CYCLES UNTIL
NO EXCEPTION (RESERVEDI
7
L
L
L
RESET
RESET TBC REGISTERS AND LOGIC
Figure 6·6. BEC Encoding Definitions
bus cycle and wait for the BEC encoding to return to zero. Each of the possible conditions is
discussed in detail in the following paragraphs.
There are three possible cases for bus exceptions. In the first case, a very early bus exception
occurs when the bus exception is asserted more than one clock cycle before DTACK is asserted.
The bus exception is acted on without any delay by the TBC and the bus cycle is terminated. In
case two, which is the typical case, the bus exception occurs in the same clock cycle as DTACK.
One delay cycle is added to the bus cycle to be sure that a bus exception has occurred before
the bus cycle is terminated. In the third case, the bus exception signal occurs on the clock after
data transfer acknowledge (DTACK) has been asserted. In this case, one clock delay is also added
before the bus cycle is terminated.
MC68824 USER'S MANUAL
MOTOROLA
II

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