Motorola MC68824 User Manual page 69

II
Check for CRC/Underrun Errors (Bit 1 of the command result area will be set if such errors
occurred.)
Check the FD Confirmation Word for each Transmitted Frame
RECEIVER TEST
Issue SET MODE 1 Command to set CACF and CUFC Mode Bits
Issue SET MODE 3 Command to set SWAP, HLEN, PS3, and RCDS Bits if Desired
Issue SET 1 WORD or 2 WORDS Command to Set Individual Address Mask to Zero (Copy all
Frames)
Issue SET 1 WORD or 2 WORDS Command to Set Group Address Mask to 'FFFF' (Copy all
Frames)
Issue SET PTP Command
Prepare Free FD and BD Pools
Issue SET 2 WORDS Commands to Initialize the Free FD and BD Pool Pointers as well as the
RX Queue Access Class 6 EOQ Pointer
Issue SET FC BD, FD, and RXITX Data Buffers if Needed
Issue SET INTERNAUEXTERNAL LOOPBACK MODE
Initialize Modem if Needed
Load CPA VALO with Pattern Word - MUST be Two Identical Bytes
Clear Done Bit in CPA Status Word
Issue RECEIVER TEST (Code is BO)
Wait for Command Confirmation which Indicates Acceptance of the Test
Wait until FD or BD Pool Empty (Bits 1 and 2 in Interrupt Status Word 0)
Issue the OFFLINE Command
Check for Received Frames' Status in the FD (Class 6)
NOTE
In order to check for command completion, the host must clear the done bit in CPA
status word before issuing a command to the TBC.
3.7 NOTIFY TBC
The two commands in this category are used to notify the TBC that a response frame is ready
when using the non-predefined RWR mechanism or to clear some interrupt status bits.
3.7.1 CLEAR INTERRUPT STATUS Command
This command is used to clear, that is negate, the interrupt request signal (IRQ) and specific status
bits in interrupt status words 0 and 1 which are located in the initialization table (see 2.2.11 Interrupt
Status Words). Before loading this command into the command register, the host must write the
mask for interrupt status word 0 into CPA VALO while the mask for interrupt status word 1 must
be loaded into CPA VAL 1. The mask consists of a '0' to leave the corresponding status bit un-
changed and a '1' to cause it to be cleared. After the TBC has cleared the desired bits, if there
remains a set, unmasked status bit in one of the status words, interrupt request will be reasserted
even if it was negated by the previous CLEAR INTERRUPT STATUS command. Upon receiving
this command the TBC will immediately negate IRQ. The status bits in the initialization table will
MOTOROLA
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MC68824 USER'S MANUAL