Tbc Write Cycle With Halt - Motorola MC68824 User Manual

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6.3.1 Normal Termination
When the BEC pins are non-asserted, the TBC operates in a normal mode and DTACK terminates
the bus cycle.
6.3.2 Halt
A logical one encoded on the BEC pins halts the TBC and the current bus cycle is terminated by
the assertion of DTACK. The TBC releases ownership of the bus and enters the idle state until the
BEC pins return to normal mode (logical zero). The halt timing diagram is shown in Figure 6-7.
The TBC rearbitrates for the bus and continues DMA operations if necessary.
SO SI S2 S3 S4 S5 S6 S7 S8 S9 SO SI S2 S3 S4 S5 SW SW
sw
SW S6 S7
CLK
(INPUT)
Al·A31
==x
(OUTPUT)
>
==x~
__________
~r-
FCO·FC3
==x
(OUTPUT)
)
==x
r-
AS
\
(OUTPUT)
f'
\~
____________ f'-
UOS. lOS
(OUTPUT)
\ f'
\ . . . . . . ______ -----JI'-
R/W
\ I
(OUTPUT)
\ _____________
~r_
00·015
<
>
(OUTPUT)
- - - - - «
>-
OTACK
\ I
(INPUT)
\ f
HALT ON
BECQ·BEC2
\
~
/
\ \ r
(INPUT)
OTACK ACTIVE BEFORE HALT
OTACK ACTIVE AFTER HALT
Figure 6-7. TBC Write Cycle with HALT
6.3.3 Bus Error
When a logical two is encoded on the BEC pins, the TBC aborts the current bus cycle and releases
bus mastership. After the BEC lines return to normal, the TBC rearbitrates for the bus to report
the bus error to the host processor by writing the address that caused the error into the DMA
dump area in the initialization table. The TBC sets the bus/address error bit in the initialization
table interrupt status word, and interrupts the host processor if enabled. A bus error condition is
shown in the Figure 6-8 timing diagram.
6.3.4 Retry
A logical three encoded on the BEC pins of the TBC terminates the current bus cycle and places
the TBC into a waiting mode. The TBC retains bus mastership by keeping BGACK asserted. When
the BEC pins return to normal, the TBC reruns the same bus cycle using the same address and
function code. Figure 6-9 shows the timing diagram for a retry operation.
MOTOROLA MC68824 USER'S MANUAL
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