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4.13 Integer Multiplier
4.13.1 Configuration of integer multiplier
The S1C63656 has a built-in unsigned-integer multiplier. This multiplier performs 8 bits × 8 bits of
multiplication or 16 bits ÷ 8 bits of division and returns the results and three flag states.
Figure 4.13.1.1 shows the configuration of the integer multiplier.
Destination register
High-order byte (DRH)
4.13.2 Multiplication mode
To perform a multiplication, set the multiplier to the source register (SR) and the multiplicand to the low-
order 8 bits (DRL) of the destination register, then write "0" to the calculation mode selection register
(CALMD). The multiplication takes 10 CPU clock cycles from writing "0" to CALMD until the 16-bit
product is loaded into the destination register (DRH and DRL). At the same time the result is loaded, the
operation flags (NF, VF and ZF) are updated.
The following shows the conditions that change the operation flag states and examples of multiplication.
N flag: Set when the MSB of DRH is "1" and reset when it is "0".
V flag: Always reset after a multiplication.
Z flag: Set when the 16-bit value in DRH/DRL is 0000H and reset when it is not 0000H.
<Examples of multiplication>
DRL (multiplicand) SR (multiplier) DRH/DRL (product) NF VF
00H
64H
C8H
C8H
S1C63656 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Integer Multiplier)
Low-order byte (DRL)
Temporary
register A
Adder
Fig. 4.13.1.1 Configuration of the integer multiplier
64H
0000H
58H
2260H
58H
44C0H
A5H
80E8H
Data bus
Source register
(SR)
Temporary
register B
Flag
(NF/VF/ZF)
ZF
0
0
1
0
0
0
0
0
0
1
0
0
EPSON
Operation
control
(CALMD)
103
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