Agilent Technologies 33250A User Manual page 296

7
Chapter 7 Tutorial
Direct Digital Synthesis
The 33250A represents amplitude values by 4,096 discrete voltage levels
(or 12-bit vertical resolution). The specified waveform data is divided
into samples such that one waveform cycle exactly fills waveform
memory (see the illustration below for a sine wave). If you create an
arbitrary waveform that does not contain exactly 16K or 64K points,
the waveform is automatically "stretched" by repeating points or by
interpolating between existing points as needed to fill waveform memory.
Since all of waveform memory is filled with one waveform cycle, each
memory location corresponds to a phase angle of 2π /16,384 radians or
2π/65,536 radians.
+2047
DAC
0
Code
4096
(90°)
-2048
Sine Wave Representation in Waveform Memory
Direct digital synthesis (DDS) generators use a phase accumulation
technique to control waveform memory addressing. Instead of using a
counter to generate sequential memory addresses, an "adder" is used
(see the following page). On each clock cycle, the constant loaded into
the phase increment register (PIR) is added to the present result in the
phase accumulator. The most-significant bits of the phase accumulator
output are used to address waveform memory. By changing the PIR
constant, the number of clock cycles required to step through the entire
waveform memory changes, thus changing the output frequency. When a
new PIR constant is loaded into the register, the waveform output
frequency changes phase continuously following the next clock cycle.
The PIR determines how fast the phase value changes with time and
ultimately controls the frequency being synthesized. More bits in the
phase accumulator result in finer frequency resolution. Since the PIR
affects only the rate of change of the phase value (and not the phase
itself), changes in waveform frequency are phase-continuous.
296
8192 16383
(180°) (360°)
12288
(270°)
Memory Address
(Phase)