Cpu & Pci Bus Control; Pci Master 0 Ws Write; Pci Delay Transaction; Sb P2P Bridge - VIA Technologies VB7009 User Manual

6.14. CPU & PCI Bus Control
Figure Figure 56 56: Illustration of the CPU & PCI Bus Control screen : Illustration of the CPU & PCI Bus Control screen
Figure Figure 56 56 : Illustration of the CPU & PCI Bus Control screen : Illustration of the CPU & PCI Bus Control screen
6.14.1.

PCI Master 0 WS Write

Settings: [Enabled, Disabled]
6.14.2.

PCI Delay Transaction

Settings: [Disabled, Enabled]
6.14.3.

SB P2P Bridge

Settings: [Disabled, Enabled]
Phoenix - AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
PCI Master 0 WS Write [Enabled]
PCI Delay Transaction [Enabled]
SB P2P Bridge [Disabled]
: Move Enter: Select +/-/PU/PD: Value
F5: Previous Values
Item Help
Menu Level
F10: Save ESC: Exit F1: General Help
F7: Optimized Defaults
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