Pcie Bus Control; Pcie Root Port; Pcie Target Link Speed; Pcie Pe0 Control - VIA Technologies VB7009 User Manual

6.12. PCIE Bus Control

Figure 54 Figure 54: Illustration of the PCIE Bus Control screen : Illustration of the PCIE Bus Control screen
Figure Figure 54 54 : Illustration of the PCIE Bus Control screen : Illustration of the PCIE Bus Control screen
6.12.1.

PCIE Root Port

Settings: [Disabled, Enabled]
6.12.2.

PCIE Target Link Speed

Settings: [Auto, Force Gen1]
6.12.3.

PCIE PE0 Control

Settings: [Disabled, Enabled]
6.12.4.

PCIE Hot-Reset Enable

Settings: [Disabled, Enabled]
6.12.5.

PCIE Root-Port-Reset Enable

Settings: [Disabled, Enabled]
6.12.6.

Maximum Payload Size

Settings: [Auto, 128 Byte]
6.12.7.

PCIE ASPM Function

Settings: [Force Disable, Auto]
Phoenix - AwardBIOS CMOS Setup Utility
PCIE Bus Control
PCIE Root Port [Enable]
PCIE Target Link Speed [Auto]
PCIE PE0 Control [Enable]
PCIE Hot-Reset Enable [Disabled]
PCIE Root-Port-Reset Enable [Disabled]
Maximum Payload Size [Auto]
PCIE ASPM Function [Auto]
: Move Enter: Select +/-/PU/PD: Value
F5: Previous Values
Item Help
Menu Level
F10: Save ESC: Exit F1: General Help
F7: Optimized Defaults
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