Agp&P2P Bridge Control; Cpu&Pci Bus Control - VIA Technologies P4M890DMP VT8237R Plus User Manual

3-6-2 AGP &P2P Bridge Control
CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
AGP Aperture Size
AGP 2.0 Mode
AGP Master 1 WS Write
AGP Master 1 WS Read
VGA Share Memory Size
Direct Frame Buffer
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
Note: Change these settings only if you are familiar with the chipset.
3-6-3 CPU&PCI Bus Control
CMOS Setup Utility – Copyright(C) 1984-2004 Award Software
PCI Master 0 WS Write
PCI Delay Transaction
VLink Mode Selection
VLink 8X Support
VIA PWR Management
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit
F5:Previous Values
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
AGP Timing Settings
128M
4X
Enabled
Enabled
64M------
Disabled
F6:Optimized Defaults
PCI Timing Settings
Disabled
Disabled
By Auto
Enabled
Enabled
F6:Optimized Defaults
36
Item Help
Menu Level >>
F1:General Help
F7:Standard Defaults
Item Help
Menu Level >>
F1:General Help
F7:Standard Defaults