Memory Architecture; Dimms - HP Integrity rx2620 User's & Service Manual

Mtransfers/s as data is clocked on both edges of the clock. The peak data bandwidth
for this memory subsystem design is 8.5 Gb/s. Load DIMMs in quads with qualified
modules. Memory is protected by data ECC, and the hardware implementation
supports chip-spare.
The minimum amount of memory supported by the server is 1 GB (four 256 MB
modules). The maximum amount of memory supported by the server is 32 GB (eight
4 GB modules).
This design does not support any nonindustry-standard DDR DIMMs. Only qualified
DIMMs are supported. Figure 5 shows a block diagram of the server memory.
Figure 5 Memory Block Diagram

Memory Architecture

The I/O ASIC memory interface supports two DDR cells. Each cell is 144 data bits
wide. The memory subsystem physical design uses a comb-filter termination scheme
for the data and the address and control buses. This topology is similar to other DDR
designs. Clocks are distributed directly from the I/O ASIC. Each clock pair drives two

DIMMs.

Memory data is protected by the ECC. Eight ECC bits per DIMM protect 64 bits of
data. The use of ECC allows correction of single-bit errors, and detection of multi-bit
errors. Only DIMMs with ECC are qualified or supported.
DIMMs
The memory subsystem supports only DDR SDRAM (Double Data Rate Synchronous
Dynamic Random Access Memory) technology utilizing industry-standard PC-1600
type DDR SDRAM DIMMs, 1.2" tall. The DIMMs use a 184-pin JEDEC standard
connector.
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