Table 5-7. Cr4 Bit Descriptions; Table 5-8. Cr3 Bit Descriptions; Table 5-9. Cr2 Bit Descriptions; Table 5-10. Cr0 Bit Descriptions - AMD Geode LX 600@0.7W Data Book

33234H
Bit Name
31:9 RSVD
8 PCE
7 PGE
6:5 RSVD
4 PSE
3 DE
2 TSC
1:0 RSVD
Bit Name
31:12 PDBR
11:0 RSVD
Bit Name
31:0 PFLA
Bit Name
31 PG
96

Table 5-7. CR4 Bit Descriptions

Description
Reserved. Set to 0 (always returns 0 when read).
Performance Counter Enable. Set PCE = 1 to make RDPMC available at nonzero privi-
lege levels.
Page Global Enable. Set PGE = 1 to make global pages immune to INVLPG instruc-
tions.
Reserved. Set to 0 (always returns 0 when read).
Page Size Extensions. Set PSE = 1 to enable 4 MB pages.
Debug Extensions. Set DE = 1 to enable debug extensions (i.e., DR4, DR5, and I/O
breakpoints).
Time Stamp Counter Instruction.
0: RDTSC instruction enabled for all CPL states.
1: RDTSC instruction enabled for CPL = 0 only.
Reserved. Set to 0 (always returns 0 when read).

Table 5-8. CR3 Bit Descriptions

Description
Page Directory Base Register. Identifies page directory base address on a 4 KB page
boundary.
Reserved. Set to 0.

Table 5-9. CR2 Bit Descriptions

Description
Page Fault Linear Address. With paging enabled and after a page fault, PFLA contains
the linear address of the address that caused the page fault.

Table 5-10. CR0 Bit Descriptions

Description
Paging Enable Bit. If PG = 1 and protected mode is enabled (PE = 1), paging is
enabled. After changing the state of PG, software must execute an unconditional branch
instruction (e.g., JMP, CALL) to have the change take effect.
AMD Geode™ LX Processors Data Book
CPU Core