Panasonic FP0 User Manual page 265

Address
FP0 C10,
FP0 T32 C14, C16,
C32, SL1
DT90052 DT9052
DT90053 -
Name
High-speed counter
control flag
Clock/calendar monitor
(hour/minute)
Descriptions
A value can be written with F0 (MV) instruction
to reset the high-speed counter, disable
counting, stop high-speed counter instruction
(F168), and clear the high-speed counter.
Control code setting
Software is not reset: H0 (0000)
Perform software reset: H1 (0001)
Disable count: H2 (0010)
Disable hardware reset: H4 (0100)
Stop pulse output (clear instruction): H8 (1000)
Perform software reset and stop pulse output:
H9 (1001)
The 16 bits of DT9052/DT90052 are allocated in
groups of four to high-speed channels 0 to 3 as
shown below.
A hardware reset disable is only effective when
using the reset input (X2 and X5). In all other
cases it is ignored.
When using pulse output, a hardware reset input
is equivalent to an home point proximate input.
Hour and minute data of the clock/calendar are
stored here.
This data is read-only data; it cannot be
overwritten.
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