Read Configuration Register Programming Values; Frequency Code Configuration Values Based On Clock Speed - Intel PXA255 Developer's Manual

Memory Controller
Table 6-17. Read Configuration Register Programming Values
Bits
2:0
5:3
6
7
8
9
10
13:11
14
15
Table 6-18
Flash. When in doubt, the higher frequency configuration and corresponding CAS latency must be
used.
Table 6-18. Frequency Code Configuration Values Based on Clock Speed (Sheet 1 of 2)
MEMCLK
Frequency
20
33
50
66
100
118
6-40
Field Name
BURST LENGTH
reserved
CLOCK CONFIGURATION
BURST SEQUENCE
WAIT CONFIGURATION
DATA OUTPUT CONFIGURATION
reserved
FREQUENCY CONFIGURATION
reserved
READ MODE
shows sample frequency configurations for programming non-SDRAM Timing Fast
SDCLK0 MDREFR:
Frequency K0DB2
20 0
33 0
50 0
25 1
66 0
33 1
50 1
59 1
Value to Program
010
8 Word Burst
000
1
Use rising edge of clock
1
Linear burst Order
(INTEL BURST ORDER IS NOT SUPPORTED)
N/A
nWAIT from the Flash device is ignored by the
processor.
0
Hold data for one clock
0
010 -> CAS Latency 3
011 -> CAS Latency 4
100 -> CAS Latency 5
101 -> CAS Latency 6
110 -> CAS Latency 7
Chosen based on the AC Characteristics - Read only
Operation section of the Flash device data sheet
0
0 - Synchronous Operation
1 - Asynchronous Operation
Valid
Frequency
Configurations
2 / 3 / 4 / 5 / 6 3 / 4 / 5 / 6 / 7
3 / 4 / 5 / 6 4 / 5 / 6 / 7
4 / 5 / 6 5 / 6 / 7
2 / 3 / 4 / 5 / 6 3 / 4 / 5 / 6 / 7
5 / 6 6 / 7
3 / 4 / 5 / 6 4 / 5 / 6 / 7
4 / 5 / 6 5 / 6 / 7
5 / 6
Intel® PXA255 Processor Developer's Manual
Corresponding
CAS Latencies
6 / 7