Timer Control Status Register (Lower) (Tccsl) - Fujitsu F2MCTM-16LX Hardware Manual

CHAPTER 13 16-Bit I/O TIMER
13.3.2

Timer Control Status Register (Lower) (TCCSL)

The timer control status register (Lower) selects the count clock and conditions for
clearing the counter, clears the counter, enables the count operation or interrupt, and
checks the interrupt request flag.
Timer Control Status Register (Lower) (TCCSL)
7
Address
TCCSL0:007942
IVF IVFE STOP
H
R/W
R/W : Read/Write
: Reset value
218
Figure 13.3-2 Timer Control Status Register (Lower) (TCCSL)
6 5 4 3 2
Rese-
CLR CLK2 CLK1 CLK0
rved
R/W R/W R/W R/W R/W
1 0
Reset value
0 0 0 0 0 0 0 0
R/W R/W
bit2 bit1 bit0
CLK2 CLK1 CLK0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
φ
: Machine clock frequency
bit3
CLR
0 No effect
1 Clear counter (TCDT = "0000
bit4
Reserved
0 Be sure to set to "0".
bit5
STOP
0 Timer operating enabled
1 Timer operating disabled (stop)
bit6
IVFE Timer overflow interrupt enable bit
0 Timer overflow interrupt disabled
1 Timer overflow interrupt enabled
bit7
Timer overflow generating flag bit
IVF
Read
0 Without timer overflow
1 With timer overflow
B
Count clock cycle selection bits
1/φ
2/φ
4/φ
8/φ
16/φ
32/φ
64/φ
128/φ
Timer clear bit
")
H
Reserved bit
Timer operation stop bit
Write
Clear this bit
No effect