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Table 111. Timing Sequence Parameters ICH4-M
Sym
T173
T176
T177
T178
T181
T182/T183
T183a
T183b
T184
T185
T186
NOTES:
1. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from
RTCRST# and the RSMRST# inactive to SUSCLK toggling may be as much as 1000 ms.
2. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
3. This transition is clocked off the 66-MHz CLK66. 1CLK66 is approximately 15 ns.
13.4.3.1.
3.3/1.5 V Power Sequencing
No power sequencing requirements exist for the associated 3.3 V/1.5 V rail of the ICH4-M chip. It is
generally good design practice to power up the core before or at the same time as the other rails.
13.4.3.2.
V
Sequencing
5REF
V
is the reference voltage for 5-V tolerance on inputs to the Intel ICH4-M. V
5REF
up before V
V
_
within 0.7 V. These rules must be followed in order to ensure proper functionality of the Intel
CC3
3
ICH4-M. Figure 135 shows a sample implementation of how to satisfy the V
®
Intel
855GM/855GME Chipset Platform Design Guide
Intel 855GM/GME Chipset Based System Power Delivery Guidelines
Description
VccSus supplies active to RSMRST# inactive
Vcc1.5, Vcc3.3, VccHI, V_CPU_IO supplies active to
PWROK, VGATE active
PWROK and VGATE active and SYS_RESET# inactive
to SUS_STAT# inactive
SUS_STAT# inactive to PCIRST# inactive
VccSus active to SLP_S5#, SUS_STAT# and PCIRST#
active
RSMRST# inactive to SUSCLK running, SLP_S5#
inactive
SLP_S5# inactive to SLP_S4# inactive
SLP_S4# inactive to SLP_S3# inactive
V_CPU_IO active to STPCLK#, CPUSLP#, STP_CPU#,
STP_PCI#, SLP_S1#, C3_STAT# inactive, and CPU
Frequency Strap signals high
PWROK and VGATE active and SYS_RESET# inactive
to SUS_STAT# inactive and CPU Frequency Straps
latched to strap values
CPU Reset Complete to Frequency Straps signals
unlatched from strap values
_
, or after V
_
within 0.7 V. Also, V
CC3
3
CC3
3
Min
Max
10
-
10
-
32
38
1
3
50
110
1
2
1
2
50
32
38
7
9
5REF
must power down after V
5REF
/ 3.3 V sequencing rule.
5REF
Units
Notes
ms
ms
RTCCLK
2
RTCCLK
2
ns
ms
1
RTCCLK
2
RTCCLK
2
ns
RTCCLK
2
CLK66
3
must be powered
_
, or before
CC3
3
261
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