Tap/Itp Checklist; Miscellaneous Checklist; Tap/Itp Signals; Clock Signals - Intel Pentium III Processor 512K Design Manual

® ®
LV Intel Pentium III Processor 512K Dual Processor Platform
Table 21. CMOS Signals (Sheet 2 of 2)
CPU Pin
SMI# (AD3)
STPCLK# (AE4)
THERMTRIP# (AE10)
7.4

TAP/ITP Checklist

There are several mechanical, electrical, and functional constraints on the debug port which must
be followed; see the Low Voltage Intel
Table 22. TAP/ITP Signals
CPU Pin
PRDY# (AE22)
PREQ# (AF19)
TCK (AD10)
TDO (AD11)
TDI (AD7)
TMS (AF7)
TRST# (AF15)
7.5

Miscellaneous Checklist

Host bus clocks are critical. Signal integrity and timing of these signals should be carefully
evaluated and simulated. Intel strongly recommends that system bus clocks be routed on signal
layers next to the ground layer and that they do not traverse multiple signal layers.
Table 23. Clock Signals
CPU Pin
BCLK (AC1)
BCLK#/CLKREF (AD1)
PICCLK (AF20)
42
Connect to second CPU and pull up through ~330 Ω to VccCMOS. May also
need to be connected to chipset or compatibility logic.
Connect to second CPU and pull up through ~330 Ω to VccCMOS. May also
need to be connected to chipset or compatibility logic.
See "Thermals" on page 38 for details
® ®
Pentium III
Pull-up resistor that matches GTL characteristic impedance to VTT, 240 Ω series
resistor to ITP.
200-300 Ω pull-up to VccCMOS and connect to ITP.
Connect to other CPU, then to 39 Ω pull-down to Gnd, and connect to ITP.
150 Ω pull-up to VccCMOS and connect to ITP from CPU0.
200-300 Ω pull-up to VccCMOS and connect to ITP.
Connect TDI from CPU0 to TDO on CPU1.
Connect to other CPU, then to 39 Ω pull-up to VccCMOS and connect to ITP.
Connect to other CPU, then to 500-680 Ω pull-down to Gnd and connect to ITP.
For single ended clocking connect BCLK to Clock Generator through 22 - 33 Ω
series resistor (OEM must simulate based on driver characteristics). Connect
BCLK# to a filtered 1.25 V supply.To reduce pin-to-pin skew, tie host clock
outputs together at the clock driver, then route to both processors and chipset.
Must be connected from the clock generator to the PICCLK pin on the CPUs.
Voltage divider circuitry should yield 2.0 V (OEM must simulate based on driver
characteristics).
Pin Connection
Processor 512K Datasheet.
Pin Connection
Pin Connection
Design Guide