Precision Time Protocol; Ptp Synchronization; Hardware Considerations - Teledyne FLIR A68 Series User Manual

Precision Time Protocol

The FLIR A68/A38 series supports IEEE 1588 Precise Time Protocol (PTP) which
provides a method for synchronizing devices over a Local Area Network (LAN). PTP is
capable of synchronizing multiple clocks to microsecond accuracy on a network
specifically designed for IEEE-1588. One device clock is considered the master, and
multiple slave devices synchronize their clocks to the master; this allows timestamps to
be consistent across the network.

PTP Synchronization

When more than one device on a LAN is PTP enabled, the IEEE 1588 protocol uses the
Best Master Clock algorithm (refer to the protocol documentation for more information)
to automatically determine which clock in the network is the most precise. It becomes
the PTP master clock. All other clocks become PTP slaves and synchronize their clocks
with the PTP master.
To synchronize, the PTP master clock periodically broadcasts synchronization messages
that the PTP slaves use to correct their local clocks. Message timestamps are used to
precisely determine the time at which a message was sent by the PTP master, and the
time at which it was received by the PTP slave. The time difference is a combination of
the clock offset (between PTP master and PTP slave) and network transmission delay.
When a PTP slave receives a synchronization message from the PTP master, it updates
its local clock in two ways:
• It adjusts its clock offset to compensate to past errors;
• It adjusts its own clock speed, to reduce future errors. When the PTP slave
detects that its clock is consistently lagging behind or accelerating ahead of the
PTP master's clock, it will adjust its own clock speed to match the PTP master's
clock speed.

Hardware Considerations

Ethernet Switches
Ethernet switches can be categorized as standard Ethernet switches and IEEE-1588
enabled Ethernet switches. A standard Ethernet switch temporarily stores packets
before sending them out. The storing time of the packet is non-deterministic and
depends on network load, resulting in packet delay variation. The packet delay
variation is the primary reason that standard Ethernet switches result in poor time
synchronization even when the master and slave clock support hardware
timestamping.
An IEEE-1588 enabled switch is a transparent clock. Using a transparent clock
improves synchronization between the master and slave and ensures that the master
and slave are not impacted by the effects of packet delay variation.
FLIR A68/A38 Series IR Camera User's Manual Features and Configuration Options • 85