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Board Hardware
CPU Debug Connector Pinout
Figure 2-10
CPU. This is done using debug tools such as Parallel Cable IV or third party tools. Refer to
the PPC405 Processor Block Manual for more information on the JTAG debug-port signals.
CPU Debug Connection to XC2VP30
The connection between the CPU debug connector and the XC2VP30 are shown in
Table
FPGA routing resources. The JTAG debug resources are not hard-wired to particular pins,
and are available for attachment in the FPGA fabric, making it possible to route these
signals to whichever FPGA pins the user prefers.
Table 2-9: CPU Debug Connection to XC2VP30
TDO
TDI
TRST_N
TCK
TMS
HALT_N
PCI Bus
The ML310 board design provides the Xilinx Virtex-II Pro access to two 33MHz/32bit PCI
buses, Primary 3.3V PCI Bus and a Secondary 5.0V PCI Bus. The FPGA is directly
connected to the Primary 3.3V PCI bus while the 5.0V PCI Bus is connected to the Primary
PCI Bus via a PCI-to-PCI Bridge. There are several PCI devices available on the PCI Buses
as well as 4 PCI add-in card Slots. All PCI Bus signals driven by the XC2VP30 comply with
the IO requirements specified in the PCI Local Bus Specification, Revision 2.2.
The majority of the ML310 features are accessed over the 33MHz/32 bit PCI Bus. The
Virtex-II Pro Power PC405 Processors can gain access to the Primary PCI Bus through the
EDK PCI Host Bridge IP. All PCI configuration and control can be performed via a PCI
Host Bridge implemented in the FPAG fabric. The Primary PCI Bus is wired so that the
FPGA fabric must used to provide PCI Bus arbitration logic. The EDK kit also provides PCI
ML310 User Guide
UG068 (v1.01) August 25, 2004
shows J12, the 16 pin header used to debug the operation of software in the
HALT_N
Figure 2-10: CPU Debug Connector (J12)
2-9. These are attached to the PowerPC™ 405 JTAG debug resources using normal
Pin Name
AH19
AJ9
AE12
AC13
AD13
AE11
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TMS
TCK
TDI
TDO
15
1
16
2
GND
TRST
VCC
UG000_05_17_082002
XC2VP30 Pin (U37)
Connector Pin (J12)
1
3
4
7
9
11
R
35
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