Appendix A: Fpga Pinouts; Fpga #1 Pinout - Xilinx Virtex-4 ML461 User Manual

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FPGA Pinouts
This appendix provides the pinouts for the four FPGAs on the Virtex-4 ML461
Development Board.

FPGA #1 Pinout

Table A-1
Table A-1: FPGA #1 Pinout
Signal Name
DDR1_DIMM_A0
DDR1_DIMM_A1
DDR1_DIMM_A2
DDR1_DIMM_A3
DDR1_DIMM_A4
DDR1_DIMM_A5
DDR1_DIMM_A6
DDR1_DIMM_A7
DDR1_DIMM_A8
DDR1_DIMM_A9
DDR1_DIMM_A10
DDR1_DIMM_A11
DDR1_DIMM_A12
DDR1_DIMM_BA0
DDR1_DIMM_BA1
DDR1_DIMM_BY0_7_CK0_N
DDR1_DIMM_BY0_7_CK0_P
DDR1_DIMM_BY8_15_CK0_N
DDR1_DIMM_BY8_15_CK0_P
DDR1_DIMM_BY8_15_CK1_N
DDR1_DIMM_BY8_15_CK1_P
DDR1_DIMM_BY8_15_CK2_N
Virtex-4 ML461 Development Board User Guide
UG079 (v1.1) September 5, 2007
lists the connections for FPGA #1 (U14).
Pin
DDR1 DIMM Memory Interface
Y9
AA9
V1
V2
T6
T7
T3
T4
U3
R4
AD5
M6
M4
Y8
AA8
N4
N5
P2
P3
P4
P5
P6
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Signal Name
DDR1_DIMM_BY8_15_CK0_N
DDR1_DIMM_BY8_15_CK0_P
DDR1_DIMM_BY8_15_CK1_N
DDR1_DIMM_BY8_15_CK1_P
DDR1_DIMM_BY8_15_CK2_N
DDR1_DIMM_BY8_15_CK2_P
DDR1_DIMM_BY8_15_CS_N
DDR1_DIMM_CAS_N
DDR1_DIMM_CKE
DDR1_DIMM_DM_DQS_BY0_H_N
DDR1_DIMM_DM_DQS_BY0_H_P
DDR1_DIMM_DM_DQS_BY1_H_N
DDR1_DIMM_DM_DQS_BY1_H_P
DDR1_DIMM_DM_DQS_BY2_H_N
DDR1_DIMM_DM_DQS_BY2_H_P
DDR1_DIMM_DM_DQS_BY3_H_N
DDR1_DIMM_DM_DQS_BY3_H_P
DDR1_DIMM_DM_DQS_BY4_H_N
DDR1_DIMM_DM_DQS_BY4_H_P
DDR1_DIMM_DM_DQS_BY5_H_N
DDR1_DIMM_DM_DQS_BY5_H_P
DDR1_DIMM_DM_DQS_BY6_H_N
Appendix A
Pin
P2
P3
P4
P5
P6
P7
N2
F1
R1
D6
E7
C7
B7
H25
H26
E24
E25
AF20
AF19
Y18
AA18
AB9
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