Synchronous Operation With Dsackx - Motorola MC68030 User Manual

Bus Operation
For asynchronous read cycles, the value of CIIN is internally latched on the rising edge of
bus cycle state 4. Refer to 7.3.1 Asynchronous Read Cycle for more details on the states
for asynchonous read cycles.
During any bus cycle terminated by DSACKx or BERR, the assertion of CBACK is
completely ignored.

7.2.9 Synchronous Operation with DSACKx

Although cycles terminated with the DSACKx signals are classified as asynchronous and
cycles terminated with STERM are classified as synchronous, cycles terminated with
DSACKx can also operate synchronously in that signals are interpreted relative to clock
edges.
The devices that use these cycles must synchronize the responses to the MC68030 clock
to be synchronous. Since they terminate bus cycles with the DSACKx signals, the dynamic
bus sizing capabilities of the MC68030 are available. In addition, the minimum cycle time for
these cycles is also three clocks.
To support those systems that use the system clock to generate DSACKx and other
asynchronous inputs, the asynchronous input setup time (parameter #47A) and the
asynchronous input hold time (parameter #47B) are given. If the setup and hold times are
met for the assertion or negation of a signal, such as DSACKx, the processor can be
guaranteed to recognize that signal level on that specific falling edge of the system clock. If
the assertion of DSACKx is recognized on a particular falling edge of the clock, valid data is
latched into the processor (for a read cycle) on the next falling clock edge provided the data
meets the data setup time (parameter #27). In this case, parameter #31 for asynchronous
operation can be ignored. The timing parameters referred to are described in MC68030EC/
D, MC68030 Electrical Specifications . If a system asserts DSACKx for the required window
around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACKx
(and/or BERR/HALT) until and throughout the clock edge that negates AS (with the
appropriate asynchronous input hold time specified by parameter #47B), no wait states are
inserted. The bus cycle runs at its maximum speed (three clocks per cycle) for bus cycles
terminated with DSACKx.
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