Motorola MC68030 User Manual page 157

Bus Operation
Table 7-4. Data Bus Requirements for Read Cycles.
(Table did not make it over in the conversion from Word)
Table 7-5 lists the combinations of SIZ0, SIZ1, A0, and A1 and the corresponding pattern of
the data transfer for write cycles from the internal multiplexer of the MC68030 to the external
data bus.
Figure 7-5 shows the transfer of a long-word operand to a word port. In the first bus cycle,
the MC68030 places the four operand bytes on the external bus. Since the address is long-
word aligned in this example, the multiplexer follows the pattern in the entry of Table 7-5
corresponding to SIZ0_SIZ1_A0_A1=0000. The port latches the data on bits D16–D31 of
the data bus, asserts DSACK1 (DSACK0 remains negated), and the processor terminates
the bus cycle. It then starts a new bus cycle with SIZ0_SIZ1_A0_A1=1010 to transfer the
remaining 16 bits. SIZ0 and SIZ1 indicate that a word remains to be transferred; A0 and A1
indicate that the word corresponds to an offset of two from the base address. The
multiplexer follows the pattern corresponding to this configuration of the size and address
signals and places the two least significant bytes of the long word on the word portion of the
bus (D16–D31). The bus cycle transfers the remaining bytes to the word-size port. Figure 7-
6 shows the timing of the bus transfer signals for this operation.
7-10 MC68030 USER'S MANUAL MOTOROLA