Motorola MC68030 User Manual page 140

Figure 6-8 shows a misaligned access of a long word at address $06 from an 8-bit port
requiring eight bus cycles to complete. Reading this long-word operand requires eight read
cycles, since accesses to all eight addresses return 8-bit port-size encodings. These cycles
fetch the two cache entries that the requested long-word spans. The first cycle requests a
long word at address $06 and accepts the first requested byte (b6). The subsequent
transfers of the first long word are performed in the following order: b7, b4, b5. The
remaining four read cycles transfer the four bytes of the second cache entry. The sequence
of access for the entire operation is b6, b7, b4, b5, b8, b9, bA, and bB.
The next example, shown in Figure 6-9, is a read of a misaligned long-word operand from
devices that return 16-bit DSACKx encodings. The processor accepts the first portion of the
operand, the word from address $06, and requests a word from address $04 to fill the cache
entry. Next, the processor reads the word at address $08, the second portion of the operand,
and stores it in the cache also. Finally, the processor accesses the word at $0A to fill the
second long-word cache entry.
Two read cycles are required for a misaligned long-word operand transfer from devices that
return 32-bit DSACKx encodings. As shown in Figure 6-10, the first read cycle requests the
long word at address $06 and latches the long word at address $04. The second read cycle
requests and latches the long word corresponding to the second cache entry at address
$08. Two read cycles are also required if STERM is used to indicate a 32-bit port instead of
the 32-bit DSACKx encoding.
Misaligned Long Word and 32-Bit DSACKx Port
If all bytes of a long word are cachable, CIIN must be negated for all bus cycles required to
fill the entry. If any byte is not cachable, CIIN must be asserted for all corresponding bus
cycles. The assertion of the CIIN signal prevents the caches from being updated during read
cycles. Write cycles (including the write portion of a read-modify-write cycle) ignore the
assertion of the CIIN signal and may cause the data cache to be altered, depending on the
state of the cache (whether or not the write cycle hits), the state of the WA bit in the CACR,
and the conditions indicated by the MMU.
The occurrence of a bus error while attempting to load a cache entry aborts the entry fill
operation but does not necessarily cause a bus error exception. If the bus error occurs on a
read cycle for a portion of the required operand (not the remaining bytes of the cache entry)
to be loaded into the data cache, the processor immediately takes a bus error exception. If
MOTOROLA
(UNABLE TO LOCATE ART)
Figure 6-8. Single Entry Mode Operation —
Misaligned Long Word and 8-Bit Port
(UNABLE TO LOCATE ART)
Figure 6-9. Single Entry Mode Operation —
Misaligned Long Word and 16-Bit Port
(UNABLE TO LOCATE ART)
Figure 6-10. Single Entry Mode Operation —
MC68030 USER'S MANUAL
On-Chip Cache Memories
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