Motorola MC68030 User Manual page 252

Bus Operation
S4
CLK
A31-A0
FC2-FC0
SIZ1-SIZ0
R/W
ECS
OCS
AS
DS
DSACK1
DSACK0
DBEN
D31-D0
BR
BG
BGACK
CONTROLLER
Figure 7-63. Bus Arbitration Operation (Bus Inactive)
The external RESET signal resets the processor and the entire system. Except for the initial
reset, RESET should be asserted for at least 520 clock periods to ensure that the processor
resets. Asserting RESET for 10 clock periods is sufficient for resetting the processor logic;
the additional clock periods prevent a reset instruction from overlapping the external RESET
signal.
7-106
BUS INACTIVE
(ARBITRATION PERMITTED
WHILE THE CONTROLLER IS
INACTIVE OR HALTED)
MC68030 USER'S MANUAL
S0
ALTERNATE MASTER CONTROLLER
MOTOROLA