Motorola MC68030 User Manual page 233

S0
CLK
A31-A0
FC2-FC0
SIZ1-SIZ0
R/W
ECS
OCS
AS
DS
DSACK1
DSACK0
DBEN
D31-D0
IPL0-IPL2
BERR
HALT
A bus error occurring during a burst fill operation is a special case. If a bus error occurs
during the first cycle of a burst, the data is ignored, the entire cache line is marked invalid,
and the burst operation is aborted. If the cycle is for an instruction fetch, a bus error
exception is made pending. This bus error is processed only if the execution unit attempts
to use either of the two words latched during the bus cycle. If the cycle is for a data fetch,
the bus error exception is taken immediately. Refer to Section 11 Instruction Execution
Timing for more information about pipeline operation.
MOTOROLA
S2 Sw Sw
WRITE WITH BUS ERROR ASSERTED
Figure 7-50. Late Bus Error with DSACKx
MC68030 USER'S MANUAL
S4
INTERNAL
PROCESSING
Bus Operation
S0 S2 S4
STACK WRITE
7-87