Motorola MC68030 User Manual page 204

Bus Operation
A31-A0
FC2-FC0
DSACK1
DSACK0
STERM
CIOUT
CBREQ
CBACK
D31-D0
Figure 7-36. Synchronous Read-Modify-Write Cycle Timing — CIIN Asserted
State 0
The processor asserts ECS and OCS in S0 to indicate the beginning of an external
operand cycle. The processor also asserts RMC in S0 to identify a read-modify-write
cycle. The processor places a valid address on A0–A31 and valid function codes on FC0–
FC2. The function codes select the address space for the operation. SIZ0–SIZ1 become
valid in S0 to indicate the operand size. The processor drives R/W high for a read cycle
7-58
S0 S1 S2 S3
CLK
SIZ1
SIZ0
R/W
RMC
ECS
OCS
AS
DS
CIIN
DBEN
MC68030 USER'S MANUAL
Si Si S4 S5 S6 S7
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