Logical Instructions - Motorola MC68030 User Manual

Enhanced 32-bit microprocessor
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Instruction Set Summary
Instruction
Operand Syntax
Dn, 〈 ea 〉
ADD
〈 ea 〉 ,Dn
〈 ea 〉 ,An
ADDA
# 〈 data 〉 , 〈 ea 〉 # 〈 data 〉 ,
ADDI
ADDQ
ADDX
Dn,Dn
–(An),–(An)
CLR
〈 ea 〉 ,Dn
CMP
〈 ea 〉 ,An
CMPA
# 〈 data 〉 , 〈 ea 〉
CMPI
CMPM
(An) +,(An) +
〈 ea 〉 ,Rn
CMP2
〈 ea〉,Dn
DIVS/DIVU
〈ea〉,Dr:Dq
〈ea〉,Dq
〈ea〉,Dr:Dq
DIVSL/DIVUL
EXT
EXTB
〈ea〉,Dn
MULS/MULU
〈ea〉,Dl
(ea〉,Dh:Dl
NEG
NEGX
〈ea〉,Dn
SUB
Dn,〈ea〉
〈ea〉,An
SUBA
SUBI
#〈data〉,〈ea〉
SUBQ
#〈data〉,〈ea〉
SUBX
Dn,Dn
–(An),–(An)

3.2.3 Logical Instructions

The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations
with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI,
and EORI) provide these logical operations with all sizes of immediate data. The TST
instruction compares the operand with zero arithmetically, placing the result in the condition
code register. Table 3–3 summarizes the logical operations.
3-6
Table 3-2. Integer Arithmetic Operations
Operand Size
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
〈 ea 〉
8, 16, 32
8, 16, 32
8, 16, 32
〈 ea 〉
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
32/16 → 16:16
64/32 → 32:32
32/32 → 32
32/32 → 32:32
8 → 16
Dn
16 → 32
Dn
8 → 32
Dn
16x16 → 32
32x32 → 32
32x32 → 64
〈ea〉
8, 16, 32
〈ea〉
8, 16, 32
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
MC68030 USER'S MANUAL
Operation
source + destination → destination
immediate data + destination → destination
source + destination + X → destination
0 → destination
destination - source
destination - immediate data
destination - source
lower bound < = Rn < = upper bound
destination/source → destination (signed or unsigned)
sign-extended destination → destination
source y destination → destination (signed or unsigned)
0 - destination → destination
0 - destination - X → destination
destination = source → destination
destination - immediate data → destination
destination - source — X → destination
MOTOROLA

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