Motorola MC68030 User Manual page 228

Enhanced 32-bit microprocessor
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Bus Operation
For STERM, the bus cycle terminations are summarized as follows (case numbers refer to
Table 7-9):
Normal Termination:
STERM is asserted; BERR and HALT remain negated (case 1).
Halt Termination:
HALT is asserted before STERM, and BERR remains negated (case 2).
Bus Error Termination:
BERR is asserted in lieu of, at the same time, or before STERM (case 3) or after
STERM (case 4), and HALT remains negated; BERR is negated at the same time or
after STERM.
Retry Termination:
HALT and BERR are asserted in lieu of, at the same time, or before STERM (case 5)
or after STERM (case 6); BERR is negated at the same time or after STERM; HALT
may be negated at the same time or after BERR.
7-82
MC68030 USER'S MANUAL
MOTOROLA

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