Motorola MC68030 User Manual page 205

and sets CIOUT to the value of the MMU CI bit in the address translation descriptor or in
the appropriate TTx register. The processor drives DBEN inactive to disable the data
buffers.
State 1
One-half clock later in S1, the processor asserts AS, indicating that the address on the
address bus is valid. The processor also asserts DS during S1. In addition, the ECS (and
OCS, if asserted) signal is negated during S1.
State 2
The selected device uses R/W, SIZ0–SIZ1, A0–A1, and CIOUT to place its information on
the data bus. Any or all of the byte sections (D24–D31, D16–D23, D8–D15, and D0–D7)
are selected by SIZ0–SIZ1 and A0–A1. During S2, the processor drives DBEN active to
enable external data buffers. In systems that use two-clock synchronous bus cycles, the
timing of DBEN may prevent its use. At the beginning of S2, the processor samples the
level of STERM. If STERM is recognized, the processor latches the incoming data. If the
selected data is not to be cached for the current cycle or if the device cannot supply 32
bits, CIIN must be asserted at the same time as STERM.
Since CIIN and STERM are synchronous signals, they must meet the synchronous nput
setup and hold times for all rising edges of the clock while AS is asserted. If STERM is
negated at the beginning of S2, wait states are inserted after S2, and STERM is sampled
on every rising edge thereafter until it is recognized. Once STERM is recognized, data is
latched on the next falling edge of the clock (corresponding to the beginning of S3).
MOTOROLA MC68030 USER'S MANUAL
Bus Operation
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