Motorola MC68030 User Manual page 249

Bus Operation
RA
State changes occur on the next rising edge of the clock after the internal signal is valid. The
BG signal transitions on the falling edge of the clock after a state is reached during which G
changes. The bus control signals (controlled by T) are driven by the processor, immediately
following a state change, when bus mastership is returned to the MC68030.
State 0, at the top center of the diagram, in which G and T are both negated, is the state of
the bus arbiter while the processor is bus master. Request R and acknowledge A keep the
arbiter in state 0 as long as they are both negated. When a request R is received, both grant
G and signal T are asserted (in state 1 at the top left). The next clock causes a change to
state 2, at the lower left, in which G and T are held. The bus arbiter remains in that state until
acknowledge A is asserted or request R is negated. Once either occurs, the arbiter changes
to the center state, state 3, and negates grant G. The next clock takes the arbiter to state 4,
at the upper right, in which grant G remains negated and signal T remains asserted. With
acknowledge A asserted, the arbiter remains in state 4 until A is negated or request R is
7-103
RA
RA
GT
STATE 1
XX
RA
XA
GT
STATE 2
RA
R - BUS REQUEST
A - BUS GRANT ACKNOWLEDGE
G - BUS GRANT
T - THREE-STATE CONTROL TO BUS CONTROL LOGIC
X - DON'T CARE
NOTE: The BG output will not be asserted while RMC is asserted.
Figure 7-61. Bus Arbitration State Diagram
MC68030 USER'S MANUAL
XA
GT
STATE 0
RA
STATE 4
XX
GT
STATE 3
GT
RX
STATE 5
GT
XX
STATE 6
RA
RA
GT
RX
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