Asynchronous Read-Modify-Write Cycle - Motorola MC68030 User Manual

7.3.3 Asynchronous Read-Modify-Write Cycle

The read-modify-write cycle performs a read, conditionally modifies the data in the
arithmetic logic unit, and may write the data out to memory. In the MC68030 processor, this
operation is indivisible, providing semaphore capabilities for multiprocessor systems. During
the entire read-modify-write sequence, the MC68030 asserts the RMC signal to indicate that
an indivisible operation is occurring. The MC68030 does not issue a bus grant (BG) signal
in response to a bus request (BR) signal during this operation. The read portion of a read-
modify-write operation is forced to miss in the data cache because the data in the cache
would not be valid if another processor had altered the value being read. However, read-
modify-write cycles may alter the contents of the data cache as described in 6.1.2 Data
Cache.
No burst filling of the data cache occurs during a read-modify-write operation.
The test and set (TAS) and compare and swap (CAS and CAS2) instructions are the only
MC68030 instructions that utilize read-modify-write operations. Depending on the compare
results of the CAS and CAS2 instructions, the write cycle(s) may not occur. Table search
accesses required for the MMU are always read-modify-write cycles to the supervisor data
space. During these cycles, a write does not occur unless a descriptor is updated. No data
is internally cached for table search accesses since the MMU uses physical addresses to
access the tables. Refer to Section 9 Memory Management Unit for information about the
MMU.
Figure 7-29 is a flowchart of the asynchronous read-modify-write cycle operation. Figure 7-
30 is an example of a functional timing diagram of a TAS instruction specified in terms of
clock periods.
State 0
The processor asserts ECS and OCS in S0 to indicate the beginning of an external
operand cycle. The processor also asserts RMC in S0 to identify a read-modify-write
cycle. The processor places a valid address on A0–A31 and valid function codes on FC0–
FC2. The function codes select the address space for the operation. SIZ0–SIZ1 become
valid in S0 to indicate the operand size. The processor drives R/W high for the read cycle
and sets 4 according to the value of the MMU CI bit in the address translation descriptor
or in the appropriate TTx register.
State 1
One-half clock later in S1, the processor asserts AS, indicating that the address on the
address bus is valid. The processor asserts DS during S1. In addition, the ECS (and OCS,
if asserted) signal is negated during S1.
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