Clock Source; Reset Source; Audio; Eeprom - ST STM3220G-EVAL User Manual

Hardware layout and configuration
2.3

Clock source

Four clock sources are available on STM3220G-EVAL evaluation board for
STM32F207IGH6 and RTC embedded:
●
X1, 25 MHz crystal for ethernet PHY with socket. It can be removed when clock is
provided by MCO pin of the MCU
●
X2, 26 MHz crystal for USB OTG HS PHY
●
X3, 32 kHz crystal for embedded RTC
●
X4, 25 MHz crystal with socket for STM32F207IGH6 microcontroller (It can be removed
from socket when internal RC clock is used.)
2.4

Reset source

The reset signal of STM3220G-EVAL evaluation board is low active and the reset sources
include:
●
Reset button B1
●
Debugging tools from JTAG connector CN14 and trace connector CN13
●
Daughterboard from CN3
●
RS-232 connector CN16 for ISP
●
ST-LINK/V2
2.5

Audio

The STM3220G-EVAL evaluation board enables stereo audio play and microphone
recording by an external headset connected on audio jack CN11. An audio DAC CS43L22 is
connected to both I2S2 port and one DAC channel while a microphone amplifier is
connected to the ADC of STM32F207IGH6. The CS43L22 can be configured via I2C1 and
the external PLL (U36) can be used to provide external clock which is connected to
I2S_CKIN pin (PC9).
Table 3.
Jumper
2.6

EEPROM

A 64KBit EEPROM is connected to the I2C1 bus of STM32F207IGH6.
Table 4.
Jumper
10/64
Audio related jumpers
JP16 Description of JP16 is in
The microphone amplifier can be disabled when JP33 is fitted.
JP33
Default setting: Not fitted
EEPROM related jumper and solder bridge
The EEPROM is in Write Protection mode when JP24 is fitted.
JP24
Default Setting: Not fitted
Doc ID 018499 Rev 2
Description
Table 10 on page 14.
Description
UM1057