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Programming Considerations
Machine Check Interrupt (MCP
2
Maskable Interrupts
2-20
∗
)
The IBC can be programmed to assert NMI when it detects either SERR
low on the PCI Local Bus or IOCHK
∗
IOCHK
is not used on the MVME1603/MVME1604. The MPC105 will
∗
assert MCP
to the processor upon detecting a high level on NMI from the
IBC.
Note that MPC105 also monitors SERR
programmed to asserted MCP
∗
or PERR
.
The MPC105 can also be programmed to assert MCP
conditions. Refer to the Programmer's Reference Guide (part number
V1600-1A/PG) for additional information on the MCP
The IBC supports 15 interrupt requests. These 15 interrupts are ISA-type
interrupts that are functionally equivalent to two 82C59 interrupt
controllers. Except for IRQ0, IRQ1, IRQ2, IRQ8
interrupt lines can be configured for either edge-sensitive or level-sensitive
mode by programming the appropriate ELCR registers in the IBC.
The IBC also supports four PCI interrupts: INT3
PIRQ Route Control Registers to allow each PCI interrupt line to be routed
to any of eleven ISA interrupt lines (IRQ0, IRQ1, IRQ2, IRQ8
IRQ13 are reserved for ISA system interrupts). Since PCI interrupts are
defined as level-sensitive, software must program the selected IRQ(s) for
level-sensitive mode. Note that more than one PCI interrupt can be routed
to the same ISA IRQ line.
The following figure shows the IBC interrupt structure. Additional details
on interrupt assignments can be found in the Programmer's Reference
Guide (part number V1600-1A/PG).
∗
low on the ISA bus. However,
∗
and PERR
∗
when it detects a low level on either SERR
∗
, and IRQ13, each of the
∗
-INT0
∗
∗
. It can be
∗
∗
under many other
∗
interrupt signal.
∗
. The IBC has four
∗
, and
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Troubleshooting
