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MVME1603/MVME1604
Single Board Computer
Installation and Use
V1600-1A/IH4

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   Summary of Contents for Motorola MVME1603

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    MVME1603/MVME1604 Single Board Computer Installation and Use V1600-1A/IH4...

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    While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.

  • Page 3

    Appendix A of this manual. The MVME1603/1604 family of Single Board Computers has two parallel branches based on two distinct versions of the base board. Both versions are populated with a number of similar plug-together components, which are listed in the following table..

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    Motorola symbol are registered trademarks of Motorola, Inc. AIX™ is a trademark of IBM Corp. PowerPC™ is a trademark of IBM Corp. and is used by Motorola with permission. All other products mentioned in this document are trademarks or registered trademarks of their respective holders.

  • Page 5

    The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

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    Low Voltage Directive (73/23/EEC). In accordance with European Community directives, a “Declaration of Conformity” has been made and is on file at Motorola, Inc. - Computer Group, 27 Market Street, Maidenhead, United Kingdom, SL6 8AE. This board product was tested in a representative system to show compliance with the above mentioned requirements.

  • Page 7: Table Of Contents

    Serial Port 4 Clock Configuration ..............1-29 Hardware Installation....................1-32 ESD Precautions ....................1-32 PM603/604 Processor/Memory Mezzanine.............1-33 RAM104 Memory Mezzanine Installation ..............1-35 MVME1603/1604 VMEmodule Installation ............1-38 MVME760 Transition Module Installation .............1-39 MVME712M Transition Module Installation ............1-42 System Considerations.....................1-45 MVME1600-001 Base Board ................1-46 MVME1600-011 Base Board ................1-47...

  • Page 8: Table Of Contents

    CHAPTER 2 Operating Instructions Introduction ....................... 2-1 Applying Power ......................2-1 ABORT Switch (S1)................... 2-1 RESET Switch (S2).................... 2-2 Front Panel Indicators (DS1 - DS6) ..............2-3 Memory Maps......................2-4 MPU Bus Memory Map ..................2-4 Normal Address Range ................2-4 PCI Local Bus Memory Map ................

  • Page 9: Table Of Contents

    Keyboard and Mouse Interface..............3-12 ISA Bridge Controller..................3-12 Real-Time Clock and NVRAM ................3-13 Programmable Timers..................3-14 Interval Timers ..................3-14 16-Bit Timers.....................3-15 VMEchip2 Timers ..................3-15 Serial Communications Interface..............3-15 Z8536 CIO Device..................3-16 Board Configuration Register ................3-16 P2 Signal Multiplexing ..................3-17 ABORT Switch (S1) ..................3-19 RESET Switch (S2) ..................3-20 Front Panel Indicators (DS1 - DS6)..............3-21 Polyswitches (Resettable Fuses)...............3-22...

  • Page 10: Table Of Contents

    ENV - Set Environment..................... 6-3 Configuring the PPCBug Parameters ..............6-3 Configuring the VMEbus Interface ..............6-12 Slave Address Decoders................6-13 APPENDIX A Related Documentation Motorola Computer Group Documents ..............A-1 Manufacturers’ Documents ..................A-3 Related Specifications ....................A-8 APPENDIX B Specifications Specifications......................B-1 Cooling Requirements ....................

  • Page 11: Table Of Contents

    Figure 1-7. J15 Clock Line Configuration ...............1-29 Figure 1-8. MVME1600-011 Serial Port 4 Clock Configuration ......1-30 Figure 1-9. P2 Adapter Component Placement ............1-31 Figure 1-10. PM603/PM604 Placement on MVME1603/1604 .......1-34 Figure 1-11. RAM104 Placement on PM603/PM604..........1-36 Figure 1-12. MVME760/MVME1600-001 Cable Connections ......1-41 Figure 1-13.

  • Page 12: Table Of Contents

    Table 2-6. VMEchip2 Memory Map (Sheet 3 of 3) ..........2-17 Table 2-7. PCI Arbitration Assignments ..............2-19 Table 2-8. IBC DMA Channel Assignments ............2-24 Table 3-1. MVME1603/MVME1604 Features ............3-1 Table 3-2. P2 Multiplexing Sequence ..............3-18 Table 3-3. Fuse Assignments by Base Board ............3-22 Table 3-4.

  • Page 13: Table Of Contents

    Table 4-23. Serial Connections—MVME1600-011 Ports 3 and 4 ......4-30 Table 5-1. Debugger Commands ................5-4 Table 5-2. Diagnostic Test Groups................5-7 Table A-1. Motorola Computer Group Documents ..........A-2 Table A-2. Manufacturers’ Documents ..............A-3 Table A-3. Related Specifications ................A-8 Table B-1. MVME1600-001/MVME1600-011 Specifications ....... B-1 Table C-1.

  • Page 15: Introduction

    The differences between the MVME1600-001 and the MVME1600-011 lie mainly in the area of I/O handling; the logic design is the same for both versions. In either case, the complete MVME1603/1604 consists of the base board plus: A processor/memory module (PM603 or PM604) with optional L2...

  • Page 16: Equipment Required

    Equipment Required Equipment Required The following equipment is required to complete an MVME1603/ 1604 system: VME system enclosure System console terminal Transition module (MVME760 for the MVME1600-001 base boards, MVME712M for the MVME1600-011) and connecting cables Disk drives (and/or other I/O) and controllers...

  • Page 17: Figure 1-1. Mvme1600-001 Base Board Block Diagram

    Hardware Preparation and Installation MOUSE DB15 68-PIN CONNECTOR TERMINATORS GRAPHICS SCSI CL-GD5446 NCR-53C825 DRAM 256Kx16 PCI LOCAL BUS TO MPU MODULE ETHERNET S82378ZB VME2PCI DECchip ISA BRIDGE BRIDGE 21040 PMC SLOT 10BT ISA BUS PC87303 DECODE SUPER I/O FUNCTION VMEchip2 ESCC MK48T18 85230...

  • Page 18: Figure 1-2. Mvme1600-011 Base Board Block Diagram

    Equipment Required HD26 HD26 RJ45 TO MPU MODULE 10BT PMC SLOT PCI LOCAL BUS EIA232 ETHERNET ESCC S82378ZB SCSI VME2PCI DECchip 85230 Z8536 ISA BRIDGE NCR-53C810 BRIDGE 21040 ISA BUS PC87303 CSRs SUPER I/O MK48T18 VMEchip2 BUFFERS P2 CONNECTOR P1 CONNECTOR 11199.00 9502 Figure 1-2.

  • Page 19: Overview Of Startup Procedure

    For more information on optional devices and equipment, refer to the documentation provided with the equipment. Power up the system. Switches and LEDs Troubleshooting the MVME1603/1604; Solving Start-Up Problems Note that the debugger prompt Using the Debugger appears. You may also wish to obtain the PPCBug Firmware Package User’s Manual listed in Appendix A.

  • Page 20: Unpacking Instructions

    The MVME1603/1604 provides software control over most options: by setting bits in control registers after installing the MVME1603/ 1604 in a system, you can modify its configuration. (The MVME1603/1604 control registers are described in Chapter 3, and/or in the MVME1603/MVME1604 Single Board Computer Programmer’s Reference Guide as listed under...

  • Page 21: Mvme1600-001 Base Board Preparation

    Hardware Preparation and Installation MVME1600-001 Base Board Preparation Figure 1-3 illustrates the placement of the switches, jumper headers, connectors, and LED indicators on the MVME1600-001. Manually configurable items on the base board include: SCSI bus terminator selection (J7) General-purpose software-readable header (J8) VMEbus system controller selection (J9) Serial Port 3 clock configuration (J10) Serial Port 4 clock configuration (J13)

  • Page 22: General-purpose Software-readable Header (j8)

    MVME1600-001 Base Board Preparation General-Purpose Software-Readable Header (J8) Header J8 provides eight readable jumpers. These jumpers can be read as a register at ISA I/O address $80000801. Bit 0 is associated with header pins 1 and 2; bit 7 is associated with pins 15 and 16. The bit values are read as a zero when the jumper is installed, and as a one when the jumper is removed.

  • Page 23: Console Port Configuration

    Hardware Preparation and Installation Console Port Configuration On the MVME1600-001 base board, either the standard serial console port ) or the on-board video (VGA) port can serve as the PPCBug COM1 firmware console port. The firmware checks for the presence of a connected keyboard and a connected mouse.

  • Page 24: Vmebus System Controller Selection (j9)

    Parity disabled (no parity) Baud rate of 9600 baud 9600 baud is the power-up default for serial ports on MVME1603/ 1604 boards. After power-up you can reconfigure the baud rate if you wish, via the PPCBug firmware’s Port Format (PF) command. Whatever the baud rate, the terminal must perform some type of hardware handshaking —...

  • Page 25: Serial Port 3 Clock Configuration (j10)

    Hardware Preparation and Installation Serial Port 3 Clock Configuration (J10) You can configure Serial port 3 on the MVME1600-001 to use the clock signals provided by the TXC signal line. Header J10 configures port 3 to either drive or receive TXC. The factory configuration has port 3 set to receive TXC.

  • Page 26: Figure 1-3. Mvme1600-001 Switches, Headers, Connectors, Fuses, Leds

    MVME1600-001 Base Board Preparation MVME 1600-001 Figure 1-3. MVME1600-001 Switches, Headers, Connectors, Fuses, LEDs 1-12...

  • Page 27: Serial Port 4 Clock Configuration (j13)

    Hardware Preparation and Installation Serial Port 4 Clock Configuration (J13) You can configure Serial port 4 on the MVME1600-001 to use the clock signals provided by the TXC signal line. Header J13 configures port 4 to either drive or receive TXC. The factory configuration has port 4 set to receive TXC.

  • Page 28: Mvme760 Transition Module Preparation

    MVME760 Transition Module Preparation Table 1-2. Remote Reset Connector J1 Interconnect Signals Signal Signal Name and Description Number Mnemonic Not used. ∗ RESETSW RESET Switch. Signal goes low when the RESET switch is pressed. It may be forced low externally for a remote reset.

  • Page 29: Configuration Of Serial Ports 3 And 4

    Hardware Preparation and Installation An Ethernet interface supporting both AUI and 10BaseT connections Two EIA-232-D asynchronous serial ports (identified as COM1 on the front panel) COM2 Two synchronous serial ports (ports 3 and 4) Configuration of Serial Ports 3 and 4 The synchronous serial ports, Serial Port 3 and Serial Port 4, are configurable via a combination of serial interface modules (SIMs) and jumper settings.

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    MVME760 Transition Module Preparation Headers J9 and J8 are used to configure Serial Port 3 and Serial Port 4, respectively. With the jumper in position 1-2, the port is configured as a DTE. With the jumper in position 2-3, the port is configured as a DCE. The jumper setting of the port should match the configuration of the corresponding SIM module.

  • Page 31: Figure 1-4. Mvme760 Connector And Header Locations

    Hardware Preparation and Installation MVME 760-001 1551 9410 Figure 1-4. MVME760 Connector and Header Locations 1-17...

  • Page 32: Mvme1600-011 Base Board Preparation

    MVME1600-011 Base Board Preparation MVME1600-011 Base Board Preparation Figure 1-5 illustrates the placement of the switches, jumper headers, connectors, and LED indicators on the MVME1600-011. Manually configurable items on the base board include: Serial Port 4 DCE/DTE selection (J7) Serial Port 4 clock selection (J8, J15, J16) Serial Port 4 I/O path selection (J9) VMEbus system controller selection (J10) Serial Port 3 I/O path selection (J13)

  • Page 33: Figure 1-5. Mvme1600-011 Switches, Headers, Connectors, Fuses, Leds

    Hardware Preparation and Installation MVME 1600-011 Figure 1-5. MVME1600-011 Switches, Headers, Connectors, Fuses, LEDs 1-19...

  • Page 34: Serial Port 4 Clock Selection (j8/15/16)

    MVME1600-011 Base Board Preparation Serial Port 4 Clock Selection (J8/15/16) The MVME1600-011 is shipped from the factory with Serial Port 4 configured for asynchronous communications (i.e., the internal clock is used). Port 4 can be configured for synchronous communications as well. It can either drive (using the internal clock) or receive (using an external clock) the Receive and Transmit clock signals.

  • Page 35: Serial Port 4 I/o Path Selection (j9)

    Hardware Preparation and Installation To complete the configuration of the clock lines, you must also set serial port 4 clock configuration header J15 on the MVME712M transition module (described later in this chapter). For details on the configuration of that header, refer to the MVME712M Transition Module section or to the user’s manual for the MVME712M (part number MVME712M).

  • Page 36: Vmebus System Controller Selection (j10)

    MVME1600-011 Base Board Preparation VMEbus System Controller Selection (J10) The MVME1600-011 is factory-configured in system controller mode (i.e., a jumper is installed across pins 2 and 3 of header J10). This means that the MVME1600-011 assumes the role of system controller at system power-up or reset.

  • Page 37: Serial Port 3 I/o Path Selection (j13)

    Hardware Preparation and Installation Serial Port 3 I/O Path Selection (J13) On the MVME1600-011, serial port 3’s I/O signals are routed to backplane connector P2 and to front panel connector J2. Header J13 determines the state of the DSR, RI, and TM signals on serial port 3. With a jumper installed on J13, DSR, RI, and TM come from the front panel.

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    MVME1600-011 Base Board Preparation Low-Order Bit Pins Definition Bit #0 (SRH0) 1—2 Reserved for future use. Bit #1 (SRH1) 3—4 With the jumper installed between pins 3 and 4 (factory configuration), the debugger uses the current user setup/operation parameters in NVRAM.

  • Page 39: Remote Status And Control

    Hardware Preparation and Installation Remote Status and Control The remote status and control connector, J4, is a keyed double-row 20-pin connector located behind the front panel of the MVME1600-011. It connects to a user-supplied external cable and carries the signals for remote reset, abort, the LEDs, and three general-purpose I/O signals.

  • Page 40: Table 1-3. Remote Reset Connector J4 Interconnect Signals

    MVME1600-011 Base Board Preparation Table 1-3. Remote Reset Connector J4 Interconnect Signals Signal Signal Name and Description Number Mnemonic +5VRMT +5 Vdc Power. Fused through fuse F1; +5 Vdc power to a user-supplied external connection. ∗ LANLED LAN LED. Signal goes low when the illuminates.

  • Page 41: Mvme712m Transition Module Preparation

    Hardware Preparation and Installation MVME712M Transition Module Preparation The MVME712M transition module (Figure 1-6) and P2 adapter board are used in conjunction with the MVME1600-011 base board. The features of the MVME712M include: A parallel printer port (through the P2 adapter) An Ethernet interface supporting AUI connections (through the P2 adapter) Four EIA-232-D multiprotocol serial ports (through the P2 adapter)

  • Page 42: Figure 1-6. Mvme712m Connector And Header Locations

    MVME712M Transition Module Preparation MVME712M Figure 1-6. MVME712M Connector and Header Locations 1-28...

  • Page 43: Serial Ports 1-4 Dce/dte Configuration

    Hardware Preparation and Installation Serial Ports 1-4 DCE/DTE Configuration Serial ports 1 through 4 are configurable as modems (DCE) for connection to terminals, or as terminals (DTE) for connection to modems. The MVME712M is shipped with the serial ports configured for DTE operation.

  • Page 44: Figure 1-8. Mvme1600-011 Serial Port 4 Clock Configuration

    MVME712M Transition Module Preparation MVME712M FRONT 64 PIN ADAPTER TRANSITION PANEL CABLE HD26 BOARD BOARD DB25 Z85230 SCC TXDB RTSB* RXDB CTSB* DCDB* TRXC4 RTXC TXCI RRXC TTXC TXCO TRXCB RTXC4 RXCI RTXCB Z8536 CIO (PB5) DTR4* RXDB (PB3) LLB4* DCDB* (PB4) RLB4* CTSB*...

  • Page 45: Figure 1-9. P2 Adapter Component Placement

    Hardware Preparation and Installation Preparation of the P2 adapter for the MVME712M consists of removing or installing the SCSI terminating resistors. Figure 1-9 illustrates the location of the resistors, fuse, and connectors. For further information on the preparation of the transition module and the P2 adapter, refer to the user’s manual for the MVME712M (part number MVME712M) as necessary.

  • Page 46: Hardware Installation

    VME chassis, and the system considerations relevant to the installation. Before installing the MVME1603/1604, ensure that the serial ports and all header jumpers are configured as desired. In most cases, the mezzanine cards—the processor/memory module, the LED mezzanine, the DRAM module, and (if applicable) the optional PCI mezzanine—are already in place on the MVME1603/1604.

  • Page 47: Pm603/604 Processor/memory Mezzanine

    Hardware Preparation and Installation PM603/604 Processor/Memory Mezzanine To install a PM603 or PM604 processor/memory mezzanine on an MVME1603/1604 main module, refer to Figure 1-10 and proceed as follows: 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground.

  • Page 48: Figure 1-10. Pm603/pm604 Placement On Mvme1603/1604

    PM603/604 Processor/Memory Mezzanine PM603/PM604 11197.00 9411 (1-2) Figure 1-10. PM603/PM604 Placement on MVME1603/1604 1-34...

  • Page 49: Ram104 Memory Mezzanine Installation

    Hardware Preparation and Installation 5. Align the standoffs on the MVME1603/1604 board with the holes at the edges of the PM603 or PM604 mezzanine, insert the Phillips screws through the holes in the mezzanine and the spacers, and tighten the screws.

  • Page 50: Figure 1-11. Ram104 Placement On Pm603/pm604

    RAM104 Memory Mezzanine Installation RAM104 PM603/PM604 Figure 1-11. RAM104 Placement on PM603/PM604 1-36...

  • Page 51

    Hardware Preparation and Installation 3. Carefully remove the MVME1603/1604 from its VMEbus card slot and lay it flat on an ESD mat, component side up, with connectors P1 and P2 facing you and the PM603/PM604 corner cutout at the upper right. The ESD mat should be on a firm, flat surface.

  • Page 52: Mvme1603/1604 Vmemodule Installation

    Install two similar screws in the bottom (tabbed) corners of the RAM104. Tighten the screws. 11. Reinstall the MVME1603/1604 assembly in its proper card slot. Be sure the module is seated properly in the backplane connectors. Do not damage or bend connector pins.

  • Page 53: Mvme760 Transition Module Installation

    Hardware Preparation and Installation – If you do not intend to use the MVME1603/1604 as system controller, it can occupy any unused double-height card slot. 4. Slide the MVME1603/1604 into the selected card slot. Be sure the module is seated properly in the P1 and P2 connectors on the backplane.

  • Page 54

    MVME760 Transition Module Installation 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure. 2.

  • Page 55: Figure 1-12. Mvme760/mvme1600-001 Cable Connections

    Hardware Preparation and Installation Note Not all peripheral cables are provided with the MVME760; you may need to fabricate or purchase certain cables. (Motorola recommends shielded cable for all peripheral connections to minimize radiation.) MVME760 MVME1600-001 ENCLOSURE BOUNDARY 1548 9412 Figure 1-12.

  • Page 56: Mvme712m Transition Module Installation

    MVME712M Transition Module Installation MVME712M Transition Module Installation The MVME712M transition module is used in conjunction with the MVME1600-011 base board. With the MVME1603/1604 installed, refer to Figure 1-13 and proceed as follows to install an MVME712M transition module: 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground.

  • Page 57

    AC or DC power source, and turn the equipment power on. Note Not all peripheral cables are provided with the MVME712M; you may need to fabricate or purchase certain cables. (Motorola recommends shielded cable for all peripheral connections to minimize radiation.) 1-43...

  • Page 58: Figure 1-13. Mvme712m/mvme1600-011 Cable Connections

    MVME712M Transition Module Installation TERMINATORS SCSI INSTALLED DEVICE SCSI DEVICE MVME712M MVME1600-011 50-CONDUCTOR CABLE 64-CONDUCTOR CABLE P2 ADAPTER TERMINATORS TERMINATORS REMOVED INSTALLED ENCLOSURE BOUNDARY cb2349301 Figure 1-13. MVME712M/MVME1600-011 Cable Connections 1-44...

  • Page 59: System Considerations

    This will cause the system to lock up. There is only one situation in which the system might lack this global bus timeout: when the MVME1603/1604 is not the system controller and there is no global bus timeout elsewhere in the system.

  • Page 60: Mvme1600-001 Base Board

    One register of the GCSR (global control/status register) set includes four bits that function as location monitors to allow one MVME1603/1604 processor to broadcast a signal to any other MVME1603/1604 processors. All eight registers are accessible from any local processor as well as from the VMEbus.

  • Page 61: Mvme1600-011 Base Board

    Hardware Preparation and Installation Note Because any device on the SCSI bus can provide TERMPWR and because the LED monitors the status of several voltages, the LED does not directly indicate the condition of any single fuse. If the LED flickers or goes out, check all the fuses (polyswitches).

  • Page 62

    System Considerations Like the MVME1600-001 base board, the MVME1600-011 supplies a signal to the 14-pin LED mezzanine connector, J1. Unlike SPEAKER_OUT the MVME1600-001 base board, the MVME1600-011 also applies the signal to the dedicated remote status and control SPEAKER_OUT connector, J4. The LED mezzanine need not be removed to cable the signal to an external speaker.

  • Page 63: Applying Power

    2Operating Instructions Introduction This chapter provides information for use of the MVME1603/1604 family of Single Board Computers in a system configuration. Here you will find the power-up procedure and descriptions of switches and LEDs; memory maps; and software initialization. Applying Power...

  • Page 64: Reset Switch (s2)

    ∗ switch resets all onboard devices; it also drives a RESET SYSRESET signal if the MVME1603/1604 is the system controller. The switch RESET may be disabled by software. The VMEchip2 includes both a global and a local reset driver. When the VMEchip2 operates as the VMEbus system controller, the reset driver ∗...

  • Page 65: Front Panel Indicators (ds1 - Ds6)

    There are six LEDs on the MVME1603/1604 front panel: , and (DS1, yellow). Checkstop; driven by the MPC603/604 status lines on the MVME1603/1604. Lights when a halt condition from the processor is detected. ∗ (DS2, yellow). Board Failure; lights when the...

  • Page 66: Memory Maps

    The memory map of devices that respond to the normal address range is shown in the following tables. The normal address range is defined by the TT signals on the MPU bus. For the MVME1603/1604, transfer types 0, 1, and 2 define the normal address range. Table 2-1 defines the entire map ($00000000 to $FFFFFFFF).

  • Page 67

    PCI Specification Revision 2.0. 2. Both Contiguous and Discontiguous mappings are supported by the MVME1603/1604. Refer to the ISA/PCI I/O Space Mapping table for more details. 3. This space is used for Direct Mapped PCI Configuration Space accesses.

  • Page 68

    Memory Maps Table 2-2 focuses on the map for the local I/O devices (accessible through the directly mapped PCI Configuration Space). Table 2-2. PCI Configuration Space Memory Map IDSEL Processor Address PCI Address Generated Definition Start Start 80800000 808007FF 00800000 008007FF Reserved 80800800...

  • Page 69

    Operating Instructions Table 2-3 focuses on the mapping of the ISA/PCI I/O space from the processor view of the memory map. Table 2-3. ISA/PCI I/O Space Memory Map ISA I/O Processor Address Function Notes Address Contiguous Discontiguous 0000-000F 8000 0000 - 8000 0000 - IBC: DMA1 Registers &...

  • Page 70

    Memory Maps Table 2-3. ISA/PCI I/O Space Memory Map (Continued) ISA I/O Processor Address Function Notes Address Contiguous Discontiguous 040B 8000 040B 8002 000B IBC: DMA1 Extended Mode Register 0410-041F 8000 0410 - 8002 0010 - IBC: DMA Scatter/Gather Command and 8000 041F 8002 001F Status Registers...

  • Page 71: Pci Local Bus Memory Map

    Operating Instructions Notes 1. All ISA I/O locations not specified in this table are reserved. 2. These locations are internally decoded by the IBC (PCI/ISA bridge). 3. These locations are internally decoded by the ISASIO (ISA Super I/O controller). 4. These locations are either not specified by the PowerPC Reference Platform (PRP) specification or are not PRP-compliant.

  • Page 72: Vmebus Memory Map

    VMEbus-to-local-bus interface. The map decoder enables you to program the starting and ending address and the modifiers to which the MVME1603/1604 responds. The VMEchip2 also includes a user-programmable map decoder for the GCSRs (global control/status registers, accessible from both the VMEbus and the local bus).

  • Page 73

    Operating Instructions Table 2-5. VME2PCI View of the Memory Map Processor Reset Value Configuration Register Name Read/Write Address (Hexadecimal) Address 80802000 00802000 PCI Vendor ID 1057h 80802002 00802002 PCI Device ID 4800h 80802004 00802004 PCI Command 0000h 80802006 00802006 PCI Status 0000h 80802008 00802008...

  • Page 74

    Memory Maps Table 2-6. Memory Map (Sheet 1 of 3) VMEchip2 VMEchip2 LCSR Base Address = $BASE + 0000 OFFSET: SLAVE ENDING ADDRESS 1 SLAVE ENDING ADDRESS 2 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER PRGM DATA MASTER ENDING ADDRESS 1 MASTER ENDING ADDRESS 2...

  • Page 75

    Operating Instructions SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER PRGM DATA MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4 MASTER ADDRESS TRANSLATION SELECT 4 MAST MAST MAST...

  • Page 76

    Memory Maps Table 2-6. VMEchip2 Memory Map (Sheet 2 of 3) VMEchip2 LCSR Base Address = $BASE + 0000 OFFSET: BGTO GLOBAL TIME OFF TIME ON TIMER TICK TIMER 1 TICK TIMER 1 TICK TIMER 2 TICK TIMER 2 SCON PURS FAIL FAIL...

  • Page 77

    Operating Instructions LOCAL PRESCALER ACCESS TIME OUT CLOCK ADJUST TIMER TIMER SELECT COMPARE REGISTER COUNTER COMPARE REGISTER COUNTER OVERFLOW OVERFLOW COUNTER 2 COUNTER 1 SCALER SPARE IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 P ERROR IRQ1E TIC TIMER 2 TIC TIMER 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL...

  • Page 78: Programming Considerations

    GENERAL PURPOSE CONTROL AND STATUS REGISTER 5 Programming Considerations Good programming practice dictates that only one MPU at a time have control of the MVME1603/1604 control registers. Of particular note are: Registers that modify the address map Registers that require two cycles to access...

  • Page 79: Pci Arbitration

    Operating Instructions PCI Arbitration There are 6 potential PCI bus masters on the MVME1603/MVME1604 single-board computer: MPC105 (PCI/MPU bus bridge and memory controller) IBC (PCI/ISA bus bridge controller) DECchip 21040 Ethernet controller 53C825 (or 53C810) SCSI controller VME2PCI ASIC (PCI/VMEchip2 interface ASIC PMC (PCI mezzanine card) slot The IBC supplies the PCI arbitration support for these six devices.

  • Page 80: Figure 2-1. Ibc Arbiter Configuration Diagram

    FIXED CONTROL BANK 2 B ROTATED CONTROL BANK 2 11187.00 9411 Figure 2-1. IBC Arbiter Configuration Diagram The PCI arbitration assignments for all PCI masters on the MVME1603/MVME1604 are as follows: Table 2-7. PCI Arbitration Assignments PCI BUS CPUREQ∗ IBCREQ∗...

  • Page 81: Interrupt Handling

    Operating Instructions Interrupt Handling The MVME1603/MVME1604 supports both maskable and non-maskable interrupts. The following figure illustrates the interrupt architecture. ∗ MPC603 MPC604 ∗ MPC105 ∗ ∗ SERR & PERR PCI INTERRUPTS ISA INTERRUPTS 11188.00 9411 Figure 2-2. MVME1603/MVME1604 Interrupt Architecture...

  • Page 82: Machine Check Interrupt (mcp*)

    PCI Local Bus or IOCHK low on the ISA bus. However, ∗ IOCHK is not used on the MVME1603/MVME1604. The MPC105 will ∗ assert MCP to the processor upon detecting a high level on NMI from the IBC.

  • Page 83: Figure 2-3. Ibc Interrupt Handler Block Diagram

    Operating Instructions TIMER1/COUNTER0 ∗ PIRQ0 IRQx PIRQ ROUTE IRQ1 CONTROL REGISTER IRQ3 INTR CONTROLLER 1 IRQ4 (INT1) ∗ PIRQ1 IRQx PIRQ ROUTE IRQ5 CONTROL REGISTER IRQ6 IRQ7 ∗ PIRQ2 IRQx PIRQ ROUTE CONTROL REGISTER IRQ8 IRQ9 ∗ PIRQ3 IRQx IRQ10 PIRQ ROUTE CONTROL REGISTER IRQ11...

  • Page 84: Vmechip2 Interrupts

    Refer to the Z85230 and the Z8536 Data Sheets for programming information and additional information about their interrupt structures. ABT (Abort) Interrupt The MVME1603/MVME1604 can be programmed to generate an ∗ interrupt to the processor via ISA Interrupt IRQ8 when the...

  • Page 85: Dma Channels

    Serial Port 4 Transmitter (Z85230 Port B Tx) High Channel 7 Not Used High Sources of Reset The MVME1603/MVME1604 SBC has six equally powerful potential sources of reset: 1. Power-on reset switch RESET ∗ function controlled by the Port 92 register in the IBC...

  • Page 86: Endian Issues

    Programming Considerations 6. When the MVME1603/MVME1604 is operating as the VMEbus ∗ System Controller, an signal will also cause a VMEbus HRESET ∗ SYSRESET Endian Issues The MVME1603/MVME1604 supports both little-endian (e.g. Windows NT) and big-endian software (e.g. AIX). The PowerPC processor and the VMEbus are inherently big-endian, while the PCI bus is inherently little- endian.

  • Page 87: Figure 2-4. Big-endian Mode

    Operating Instructions BIG-ENDIAN PROGRAM DRAM MPC105 BIG ENDIAN N-WAY BYTE SWAP LITTLE ENDIAN VME2PCI LITTLE ENDIAN N-WAY BYTE SWAP BIG ENDIAN VMEchip2 VMEbus 11190.00 9411 Figure 2-4. Big-Endian Mode 2-25...

  • Page 88: Figure 2-5. Little-endian Mode

    Programming Considerations LITTLE-ENDIAN PROGRAM LITTLE ENDIAN BIG ENDIAN EA MODIFICATION (XOR) DRAM MPC105 BIG ENDIAN EA MODIFICATION LITTLE ENDIAN VME2PCI LITTLE ENDIAN N-WAY BYTE SWAP BIG ENDIAN VMEchip2 VMEbus 11191.00 9411 Figure 2-5. Little-Endian Mode 2-26...

  • Page 89: Pci Domain

    Operating Instructions PCI Domain The PCI bus is inherently little-endian and all devices connected directly to PCI will operate in little-endian mode, regardless of the mode of operation in the processor’s domain. 53C825 or 53C810(SCSI) SCSI is byte-stream-oriented; the byte having the lowest address in memory is the first one to be transferred regardless of the endian mode.

  • Page 90

    Programming Considerations In big-endian mode, byte-swapping is performed first by the VME2PCI and then by the MPC105. The result has the desirable effect of being transparent to the big-endian software. In little-endian mode, however, software must take the byte-swapping effect of the VME2PCI and the address reverse-rearranging effect of the MPC105 into account.

  • Page 91

    Detailed descriptions of other MVME1603/MVME1604 blocks, including programmable registers in the ASICs and peripheral chips, can be found in the Programmer’s Reference Guide (part number V1600-1A/PG). Refer to it for a functional description of the MVME1603/MVME1604 in greater depth. Features...

  • Page 92

    Features Table 3-1. MVME1603/MVME1604 Features (Continued) Feature Description Models Real-time clock 8KB NVRAM with RTC and battery backup All models (SGS-Thomson M48T18) Switches All models RESET ABORT Status LEDs Six: All models Tick timers Four programmable 16-bit timers (one in All models S82378ZB ISA bridge;...

  • Page 93: General Description

    256KB L2 cache memory is available as an option on certain models of the MVME1603 and the MVME1604. The MVME1603/1604 family has two parallel branches based on two distinct versions (MVME1600-001 and MVME1600-011) of the base board. The differences between the MVME1600-001 and the MVME1600-011 lie mainly in the area of I/O handling;...

  • Page 94: Block Diagram

    VME package. Its flexible mezzanine architecture allows relatively easy upgrades of the processor and/or memory. A key feature of the MVME1603/MVME1604 family is the PCI (Peripheral Component Interconnect) bus. In addition to the on-board local bus peripherals, the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PMC (PCI Mezzanine Card).

  • Page 95: Figure 3-1. Mvme1603/mvme1604 Block Diagram

    SCSI VIDEO DECchip PMC SLOT VMEchip2 NCR-53C8xx CL-GD5446 21040 MVME1600-001 / 011 BASE BOARD NOTES : 1. SHADED BOXES ARE MVME1600-001 FEATURES ONLY. 2. SCSI CONTROLLER IS NCR-53C825 ON MVME1600-001, NCR-53C810 ON -011. 11186.00 9606 Figure 3-1. MVME1603/MVME1604 Block Diagram...

  • Page 96: Scsi Interface

    The MVME1600-001 base board provides onboard SCSI bus termination. The terminators can be enabled or disabled by a jumper (J7—described in Chapter 1). If the SCSI bus ends at the MVME1603/MVME1604 module, then SCSI termination must be enabled. +5Vdc power to the SCSI bus...

  • Page 97: Ethernet Interface

    08003E2xxxxx is stored in NVRAM. At an address of $FFFC1F2C, the upper four bytes (08003E2x) can be read. At an address of $FFFC1F30, the lower two bytes (xxxx) can be read. The MVME1603/MVME1604 debugger, PPCBug, has the capability to retrieve or set the Ethernet station...

  • Page 98: Graphics Interface

    MVME1603/MVME1604 Programmer’s Reference Guide for detailed programming information. Note The MVME1603/MVME1604 will support either AUI or 10BaseT Ethernet connections, but not both at the same time. To switch from one type to the other, do the following: 1.

  • Page 99: Pci Mezzanine Interface

    Reference Manual for detailed programming information. PCI Mezzanine Interface A key feature of the MVME1603/MVME1604 family is the PCI (Peripheral Component Interconnect) bus. In addition to the on-board local bus devices (SCSI, Ethernet, graphics, etc.), the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PMC (PCI...

  • Page 100: Vmebus Interface

    VMEchip2 and VME2PCI discussions in the MVME1603/MVME1604 Programmer’s Reference Guide. ISA Super I/O Device (ISASIO) The MVME1603/MVME1604 uses a PC87303 ISASIO chip from National Semiconductor to implement certain segments of the P2 and front-panel I/O: Two asynchronous serial ports (COM1 and COM2) via P2 and...

  • Page 101: Parallel Port

    IRQ4 and COM2 to IRQ3. You can change the default configuration by reprogramming the ISASIO device. For detailed programming information, refer to the PCI and ISA bus discussions in the MVME1603/MVME1604 Programmer’s Reference Guide and to the vendor documentation for the ISASIO device. Parallel Port The parallel port is an IEEE P1284 printer interface implemented with the ISASIO device.

  • Page 102: Disk Drive Controller

    ISA Bridge Controller The MVME1603/MVME1604 uses an Intel S82378ZB bridge controller to supply the interface between the PCI local bus and the ISA system I/O bus (diagrammed in Figure 1-1 and Figure 1-2 for the two base boards).

  • Page 103: Real-time Clock And Nvram

    $00800800 in the PCI Configuration area. Real-Time Clock and NVRAM The MVME1603/MVME1604 employs an SGS-Thomson surface-mount M48T18 RAM and clock chip to provide 8KB of non-volatile static RAM and a real-time clock. This chip provides a clock, oscillator, crystal, power...

  • Page 104: Programmable Timers

    SPEAKER_OUT cabled to an external speaker via the remote reset connector). The interval timers use the OSC clock input as their clock source. The MVME1603/MVME1604 module drives the OSC pin with a 14.31818 MHz clock source. 3-14...

  • Page 105: Bit Timers

    Functional Description 16-Bit Timers Four 16-bit timers are available on the MVME1603/MVME1604. The ISA bridge controller supplies one 16-bit timer; the Z8536 CIO device provides the other three. For information on programming these timers, refer to the data sheets for the S82378ZB ISA bridge controller and the Z8536 CIO device.

  • Page 106: Z8536 Cio Device

    Z85230 according to the interrupt source. Interrupt request levels are programmed via the ISA bridge controller. Refer to the Z85230 data sheet and to the MVME1603/ MVME1604 Programmer’s Reference Guide for further information. Z8536 CIO Device...

  • Page 107: P2 Signal Multiplexing

    Functional Description Board Configuration Register - $0802 ∗ ∗ ∗ ∗ ∗ ∗ ∗ FIELD GIOP SCCP PMCP VMEP GFXP LANP SCSIP OPER RESET ∗ GIOP Transition module present. If set, the MVME760 transition module is not connected. If cleared, the MVME760 module is connected.

  • Page 108: Table 3-2. P2 Multiplexing Sequence

    Block Diagram Four signals are involved in the P2 multiplexing function: MXDO, MXDI, ∗ MXCLK, and MXSYNC MXDO is a time-multiplexed data output line from the main board and MXDI is a time-multiplexed line from the MVME760 module. MXCLK ∗ is a 10MHz bit clock for the MXDO and MXDI data lines.

  • Page 109: Abort Switch (s1)

    The interrupt is normally used to abort program execution and return control to the PPCBug debugger firmware located in the MVME1603/1604 EPROM and Flash memory. The interrupt signal reaches the processor module via ∗...

  • Page 110

    GCSR. SYSRESET Note For an MVME1603/1604 without the VMEbus option (i.e., with no VMEchip2), the LCSR control bit is not available to reset the module. In this case, the watchdog timer is allowed to time out to reset the MVME1603/1604.

  • Page 111

    There are six LEDs on the MVME1603/1604 front panel: , and (DS1, yellow). Checkstop; driven by the MPC603/604 status lines on the MVME1603/1604. Lights when a halt condition from the processor is detected. ∗ (DS2, yellow). Board Failure; lights when the...

  • Page 112: Polyswitches (resettable Fuses)

    Block Diagram Polyswitches (Resettable Fuses) The MVME1600-001 and MVME1600-011 base boards draw fused +5Vdc, +12Vdc, and –12Vdc power from the VMEbus backplane through connectors P1 and P2. The 3.3Vdc power (used by the ISA Super I/O device on the base board, and by the PM603 or PM604 processor/memory mezzanine) is derived on-board from the +5Vdc.

  • Page 113

    Functional Description Note Because any device on the SCSI bus can provide TERMPWR and because the LED monitors the status of several voltages, the LED does not directly indicate the condition of any single fuse. If the LED flickers or goes out, check all the fuses (polyswitches).

  • Page 114: Speaker Control

    Block Diagram Speaker Control The MVME1600-001 base board supplies a signal to the SPEAKER_OUT 14-pin combined LED-mezzanine/remote-reset connector, J1. When J1 is used as a remote reset connector with the LED mezzanine removed, the signal can be cabled to an external speaker to obtain a SPEAKER_OUT beep tone.

  • Page 115

    Functional Description MPC604 boards have double-wide front panels to accommodate a heat sink on the PowerPC604 that protrudes into the adjacent VME slot. The PM603/PM604 module accommodates additional memory. RAM104 modules of 8, 16, 32, or 64MB DRAM are available for memory expansion.

  • Page 116: Ram104 Memory Module

    There is no parity or ECC protection on the DRAM. The addition of the memory module on the processor/memory module makes a stack three boards high. An MVME1603 SBC maintains a single VME slot width with this stacking, although it does brush the inter-card buffer zone.

  • Page 117: Mvme760 Transition Module

    Functional Description MVME760 Transition Module The MVME760 transition module (Figure 1-4) is used in conjunction with the MVME1600-001 base board. The features of the MVME760 include: A parallel printer port An Ethernet interface supporting both AUI and 10BaseT connections Two EIA-232-D asynchronous serial ports (identified as COM1 on the front panel) COM2...

  • Page 118: Mvme712m Transition Module

    Block Diagram MVME712M Transition Module The MVME712M transition module (Figure 1-6) and P2 adapter board are used in conjunction with the MVME1600-011 base board. The features of the MVME712M include: A parallel printer port (through the P2 adapter) An Ethernet interface supporting AUI connections (through the P2 adapter) Four EIA-232-D multiprotocol serial ports (through the P2 adapter) An SCSI interface (through the P2 adapter) for connection to both...

  • Page 119: Connector Pin Assignments

    4Connector Pin Assignments This chapter summarizes the pin assignments for the following groups of interconnect signals for the MVME1603/MVME1604: Connectors with pin assignments common to both the MVME1600- 001 and MVME1600-011 base boards Connector Table LED Mezzanine connector MPU Mezzanine connector...

  • Page 120: Common Connectors

    The following tables furnish pin assignments only. For detailed descriptions of the various interconnect signals, consult the support information documentation package for the MVME1603/ MVME1604 SBC or the support information sections of the MVME760 or MVME712M transition module documentation as necessary.

  • Page 121: Led Mezzanine Connector

    Connector Pin Assignments LED Mezzanine Connector A 16-pin connector (J1 on the base board) supplies the interface between the base board and the LED mezzanine module. On the base board, this connector is a 2x7 header. On the LED mezzanine, it is a 2x7 surface- mount socket strip.

  • Page 122: Table 4-2. Mpu Mezzanine Connector

    Common Connectors Table 4-2. MPU Mezzanine Connector PCICLK1 PCICLK2 PCICLK3 PCICLK4 ∗ ∗ CKSTOP CPULED ∗ ∗ IBCINT ABORT ∗ ∗ LANINT VME2PCIINT ∗ ∗ SCSIINT GRINT ∗ PMCIRQ KBIRQ MOUSEIRQ COM1IRQ COM2IRQ PARPTIRQ ∗ ∗ CIO_IRQ SCC_IRQ ∗ ∗ FLPYIRQ ∗...

  • Page 123

    Connector Pin Assignments Table 4-2. MPU Mezzanine Connector (Continued) Reserved ∗ ∗ CBE0 CBE1 ∗ ∗ CBE2 CBE3 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI_RESV5 PAR64 ∗...

  • Page 124: Cpu Connector

    Common Connectors CPU Connector A 190-pin connector (J2 on the PM603/PM604 processor/memory mezzanine module) provides access to the processor bus (MPU bus) and some MPC105 bridge/memory controller signals. It can be used to add L2 cache memory (refer to the PM603/PM604 User’s Manual) or to upgrade the processor.

  • Page 125: Table 4-3. Cpu Connector

    Connector Pin Assignments Table 4-3. CPU Connector PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PA_PAR0 PA_PAR1 PA_PAR2 PA_PAR3 ∗ ∗ RSRV PD10 PD11 PD12 PD13 PD14 PD15 PD16...

  • Page 126

    Common Connectors Table 4-3. CPU Connector (Continued) PD38 PD39 PD40 PD41 PD42 PD43 PD44 PD45 PD46 PD47 PD48 PD49 PA50 PD51 PD52 PD53 PD54 PD55 PD56 PD57 PD58 PD59 PD60 PD61 PD62 PD63 PDPAR0 PDPAR1 PDPAR2 PDPAR3 PDPAR4 PDPAR5 PDPAR6 PDPAR7 No Connection No Connection...

  • Page 127

    Connector Pin Assignments Table 4-3. CPU Connector (Continued) ∗ ∗ L2ADSC IBCINT ∗ ∗ L2BAA MCHK ∗ ∗ L2DIRTYI ∗ ∗ L2DIRTYO CKSTPI ∗ ∗ L2DOE CKSTPO ∗ L2DWE1 HALTED (N/C) ∗ ∗ L2HIT TLBISYNC L2TALE TBEN ∗ ∗ L2TALOE SUSPEND ∗...

  • Page 128: Dram Expansion Connectors

    Common Connectors DRAM Expansion Connectors Two 100-pin connectors (J3 and J4 on the PM603/PM604 processor/memory mezzanine module) supply the interface between the processor/memory mezzanine and the RAM104 DRAM mezzanine. The pin assignments are listed in the following two tables. Table 4-4. DRAM Mezzanine—Connector 1 ∗...

  • Page 129: Pci Mezzanine Card Connectors

    Connector Pin Assignments Table 4-5. DRAM Mezzanine—Connector 2 ∗ BWEB3 BMD48 BMD24 BMD49 BMD25 BMD50 BMD26 BMD51 +3.3V BMD27 +3.3V BMD52 BMD28 BMD53 BMD29 BMD54 BMD30 BMD55 +3.3V BMD31 +3.3V BMD56 BMD32 BMD57 BMD33 BMD58 BMD34 BMD59 +3.3V BMD35 +3.3V BMD60 BMD36 BMD61...

  • Page 130: Table 4-6. Pci Mezzanine Card Connector

    Common Connectors Table 4-6. PCI Mezzanine Card Connector ∗ –12V +12V TRST ∗ INTA TDO2 ∗ ∗ INTB INTC TDO1 ∗ PNCP Not Used ∗ INTD Not Used Not Used Not Used Not Used Pull-up +3.3V ∗ LBRESET Pull-down ∗ PMCGNT +3.3V Pull-down...

  • Page 131: Table 4-7. Vmebus Connector P1

    Connector Pin Assignments Table 4-7. VMEbus Connector P1 Row A Row B Row C ∗ VBBSY ∗ VBCLR ∗ VACFAIL VD10 ∗ VBGIN0 VD11 ∗ VBGOUT0 VD12 ∗ VBGIN1 VD13 ∗ VBGOUT1 VD14 ∗ VBGIN2 VD15 ∗ VBGOUT2 ∗ ∗ VSYSCLK VBGIN3 VSYSFAIL...

  • Page 132: Ethernet 10baset Connector

    Common Connectors Ethernet 10BaseT Connector The MVME1603/MVME1604 provides both AUI and 10BaseT LAN connections. The 10BaseT interface is implemented with a standard RJ45 socket. For MVME1600-001 base boards, the RJ45 connector is located on the MVME760 transition module; for MVME1600-011 base boards, it is located on the front panel of the board itself.

  • Page 133: Disk Drive Connector

    Connector Pin Assignments Disk Drive Connector A 34-pin connector (J6 on the base board) supplies the interface between the base board and an optional disk drive. The disk drive may take the form of a mezzanine board or a separate module. The pin assignments are listed in the following table.

  • Page 134: Mvme1600-001 Connectors

    MVME1600-001 Connectors MVME1600-001 Connectors The following tables summarize the pin assignments of connectors that are specific to MVME1603/MVME1604 modules based on the MVME1600- 001 base board, used with MVME760 transition modules. VMEbus Connector P2 Two 96-pin connectors (P1 and P2) supply the interface between the base board and the VMEbus.

  • Page 135: Table 4-10. Scsi Connector

    Connector Pin Assignments Table 4-10. SCSI Connector ∗ SCSID12 ∗ SCSID13 ∗ SCSID14 ∗ SCSID15 SCSCDP ∗ SCSID0 1∗ SCSID ∗ SCSID2 ∗ SCSID3 ∗ SCSID4 ∗ SCSID5 ∗ SCSID6 ∗ SCSID7 SCSCDP0 SCSI_TP SCSI_TP SCSI_TP SCSI_TP No Connection No Connection ∗...

  • Page 136: Graphics Connector

    MVME1600-001 Connectors Graphics Connector The MVME1600-001 base board has a DB15 graphics connector located on the front panel. The pin assignments for the graphics connector are listed in the following table. Table 4-11. Graphics Connector GIRED GIGREEN GIBLUE GIP2 No Connection GIP0 GIP1 GIHSYNC...

  • Page 137: Keyboard And Mouse Connectors

    Connector Pin Assignments Keyboard and Mouse Connectors The MVME1600-001 base board has two 6-pin circular DIN connectors for the keyboard and mouse located on the front panel. The pin assignments for those connectors are listed in the following two tables. Table 4-12.

  • Page 138: Ethernet Aui Connector

    MVME1600-001 Connectors Ethernet AUI Connector The MVME1603/MVME1604 provides both AUI and 10BaseT LAN connections. For the MVME1600-001 base board, the AUI interface is implemented with a DB15 (J11) connector located on the MVME760 transition module. The pin assignments are listed in the following table.

  • Page 139: Parallel I/o Connector

    Connector Pin Assignments Parallel I/O Connector Both versions of the base board provide parallel I/O connections. For the MVME1600-001 base board, the parallel interface is implemented with an IEEE P1284 36-pin connector (J10) located on the MVME760 transition module. The pin assignments are listed in the following table. Table 4-15.

  • Page 140: Serial Ports 1 And 2

    MVME1600-001 Connectors Serial Ports 1 and 2 The MVME1603/MVME1604 provides both asynchronous (ports 1 and 2) and synchronous/asynchronous (ports 3 and 4) serial connections. For the MVME1600-001 base board, the asynchronous interface is implemented with a pair of DB9 connectors (...

  • Page 141: Serial Ports 3 And 4

    Connector Pin Assignments Serial Ports 3 and 4 For the MVME1600-001 base board, the synchronous/ asynchronous interface for ports 3 and 4 is implemented with a pair of 26-pin 3M-type ribbon connectors (J7 and J2) located on the board surface of the MVME760 transition module.

  • Page 142: Mvme1600-011 Connectors

    MVME1600-011 Connectors MVME1600-011 Connectors The following tables summarize the pin assignments of connectors that are specific to MVME1603/MVME1604 modules based on the MVME1600- 011 base board, used with MVME712M transition modules. VMEbus Connector P2 Two 96-pin connectors (P1 and P2) supply the interface between the base board and the VMEbus.

  • Page 143: Table 4-18. Vmebus Connector P2

    Connector Pin Assignments Table 4-18. VMEbus Connector P2 Row A Row B Row C ∗ SCSID0 SCSID1 ∗ ∗ SCSID2 RETRY SCSID3 VA24 ∗ SCSID4 VA25 SCSID5 VA26 SCSID6 VA27 +12VLAN SCSID7 VA28 PR_STD SCSIDPO VA29 PR_DATA0 ∗ SATN VA30 PR_DATA1 ∗...

  • Page 144: Table 4-19. Scsi Connector (mvme712m)

    MVME1600-011 Connectors Table 4-19. SCSI Connector (MVME712M) DB00∗ DB01∗ DB02∗ DB03∗ DB04∗ DB05∗ DB06∗ DB07∗ DBP∗ Reserved TERMPWR ATN∗ BSY∗ ACK∗ RST∗ MSG∗ SEL∗ D/C∗ REQ∗ O/I∗ 4-26...

  • Page 145

    Connector Pin Assignments Ethernet AUI Connector The MVME1603/MVME1604 provides both AUI and 10BaseT LAN connections. For the MVME1600-011 base board, the AUI interface is implemented with a DB15 connector located on the MVME712M transition module. The pin assignments are listed in the following table.

  • Page 146

    MVME1600-011 Connectors Parallel I/O Connector Both versions of the base board provide parallel I/O connections. For the MVME1600-011 base board, the parallel interface is implemented with a 36-pin Centronics-type socket connector located on the MVME712M transition module. The pin assignments are listed in the following table. Table 4-21.

  • Page 147: Serial Ports 1-4

    Connector Pin Assignments Serial Ports 1-4 For the MVME1600-011 base board, the interface for asynchronous ports 1 and 2 and for synchronous/asynchronous ports 3 and 4 is implemented with four EIA-232-D DB25 connectors (J7-J10) located on the front panel of the MVME712M transition module. In addition, ports 3 and 4 have HD26 front panel connectors (J2, J3) on the base board.

  • Page 148: Table 4-23. Serial Connections—mvme1600-011 Ports 3 And 4

    No Connection SPnTXCO SPnTM No Connection For detailed descriptions of the various interconnect signals, consult the support information documentation package for the MVME1603/MVME1604 SBC or the support information sections of the MVME760 or MVME712M transition module documentation as necessary. 4-30...

  • Page 149: Overview

    5PPCBug Overview The PowerPC debugger, PPCBug, is a powerful evaluation and debugging tool for systems built around Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation. The PowerPC debugger provides a high degree of functionality and user friendliness, and yet stresses portability and ease of maintenance.

  • Page 150: Memory Requirements

    (e.g., GO), then control may or may not return to PPCBug, depending on the outcome of the user program. The PPCBug is similar to previous Motorola firmware debugging packages (e.g., MVME147Bug, MVME167Bug, MVME187Bug), with differences due to microprocessor architectures. These are primarily...

  • Page 151: Using The Debugger

    PPCBug Using the Debugger PPCBug is command-driven; it performs its various operations in response to commands that you enter at the keyboard. When the PPC1-Bug prompt appears on the screen, the debugger is ready to accept debugger commands. When the PPC1-Diag prompt appears on the screen, the debugger is ready to accept diagnotics commands.

  • Page 152: Debugger Commands

    Using the Debugger Debugger Commands The individual debugger commands are listed in the following table. The commands are described in detail in the PPCBug Firmware Package User’s Manual, Chapter 2 Note You can list all the available debugger commands by entering the Help (HE) command alone.

  • Page 153

    PPCBug Table 5-1. Debugger Commands (Continued) Command Description GEVDUMP Global Environment Variable(s) Dump GEVEDIT Global Environment Variable Edit GEVINIT Global Environment Variable Initialization GEVSHOW Global Environment Variable(s) Display Go to Next Instruction Go Execute User Program Go to Temporary Breakpoint Help I/O Control for Disk I/O Inquiry...

  • Page 154

    Using the Debugger Table 5-1. Debugger Commands (Continued) Command Description Offset Registers Display/Modify Printer Attach NOPA Printer Detach PBOOT Bootstrap Operating System Port Format NOPF Port Detach PFLASH Program FLASH Memory Put RTC into Power Save Mode ROMboot Enable NORB ROMboot Disable Register Display REMOTE...

  • Page 155: Diagnostic Tests

    The individual diagnostic test sets are listed in the following table. The diagnostics are described in the PPC1Bug Diagnostics Manual. Table 5-2. Diagnostic Test Groups Test Set Description Applicability MVME1603/1604 DEC21040 DECchip 21040 Ethernet Controller Tests MVME1603/1604 I82378 i82378 PCI/ISA Bridge Tests...

  • Page 156

    Using the Debugger...

  • Page 157

    6CNFG and ENV Commands Overview You can use the factory-installed debug monitor, PPCBug, to modify certain parameters contained in the PowerPC board’s Non-Volatile RAM (NVRAM), also known as Battery Backed-up RAM (BBRAM). The Board Information Block in NVRAM contains various elements concerning operating parameters of the hardware.

  • Page 158: Cnfg - Configure Board Information Block

    NVRAM. The board information block contains various elements detailing specific operational parameters of the PowerPC board. The board structure for the PowerPC board is as shown in the following example for an MVME1603-001: Board (PWA) Serial Number = “MOT001673590 ”...

  • Page 159: Env - Set Environment

    CNFG and ENV Commands ENV - Set Environment Use the ENV command to view and/or configure interactively all PPCBug operational parameters that are kept in Non-Volatile RAM (NVRAM). Refer to the PPCBug Firmware Package User’s Manual for a description of the use of ENV. Additional information on registers in the VMEchip2 and VME2PCI ASICs that affect these parameters is contained in your PowerPC board programmer’s reference guide.

  • Page 160

    ENV - Set Environment Remote Start Method Switch [G/M/B/N] = B? The Remote Start Method Switch is used when the MVME1603/MVME1604 is cross-loaded from another VME-based CPU, to start execution of the cross-loaded program. Use the Global Control and Status Register (GCSR,...

  • Page 161

    CNFG and ENV Commands Negate VMEbus SYSFAIL* Always [Y/N] = N? ∗ Negate the VMEbus SYSFAIL signal during board initialization. ∗ Negate the VMEbus SYSFAIL signal after successful completion or entrance into the bug command monitor. (Default) Local SCSI Bus Reset on Debugger Startup [Y/N] = Y? Local SCSI bus is reset on debugger setup.

  • Page 162

    ENV - Set Environment NVRAM Bootlist (GEV.fw-boot-path) Boot Abort Delay = 5? The time in seconds that a boot from the NVRAM boot list will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the key.

  • Page 163

    CNFG and ENV Commands Auto Boot Controller LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of disk/tape controller modules currently supported by PPCBug. (Default = $00) Auto Boot Device LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of disk/tape devices currently supported by PPCBug.

  • Page 164

    ENV - Set Environment ROM Boot Enable search of VMEbus [Y/N] = N? VMEbus address space, in addition to the usual areas of memory, will be searched for a ROMboot module . VMEbus address space will not be accessed by ROMboot.

  • Page 165

    CNFG and ENV Commands Network Auto Boot Controller LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of disk/tape controller modules currently supported by PPCBug. (Default = $00) Network Auto Boot Device LUN = 00? Refer to the PPCBug Firmware Package User’s Manual for a listing of disk/tape controller modules currently supported by PPCBug.

  • Page 166

    ENV - Set Environment Memory Size Enable [Y/N] = Y? Memory will be sized for Self Test diagnostics. (Default) Memory will not be sized for Self Test diagnostics. Memory Size Starting Address = 00000000? The default Starting Address is $00000000. Memory Size Ending Address = 02000000? The default Ending Address is the calculated size of local memory.

  • Page 167

    PIRQ0/1/2/3. The default is determined by system type. For details on PCI/ISA interrupt assignments and for suggested values to enter for this parameter, refer to the Maskable Interrupts section of Chapter 4 in the MVME1603/ MVME1604 Programmer’s Reference Guide. 6-11...

  • Page 168: Configuring The Vmebus Interface

    Configuring the VMEbus Interface ENV asks the following series of questions to set up the VMEbus interface for the MVME1603/MVME1604 series modules. To perform this configuration, you should have a working knowledge of the VME2PCI and VMEchip2 ASICs as described in the Programmer’s Reference Guide.

  • Page 169: Slave Address Decoders

    (bits 31-16). Bits 15-00 will be zero. (Default = $D0000000) Slave Address Decoders The slave address decoders are used to allow another VMEbus master to access a local resource of the MVME1603/1604. There are two slave address decoders set. They are set up as follows: 6-13...

  • Page 170

    ENV - Set Environment Slave Enable #1 [Y/N] = Y? Yes, set up and enable the Slave Address Decoder #1. (Default) Do not set up and enable the Slave Address Decoder Slave Starting Address #1 = 00000000? Base address of the local resource that is accessible by the VMEbus. (Default = $0, base of local memory) Slave Ending Address #1 = 03FFFFFF? Ending address of the local resource that is accessible by the VMEbus.

  • Page 171

    CNFG and ENV Commands Base address of the local resource that is accessible by the VMEbus. (Default = $00000000) Slave Ending Address #2 = 00000000? Ending address of the local resource that is accessible by the VMEbus. (Default = $00000000) Slave Address Translation Address #2 = 00000000? Enables the VMEbus address and the local address to differ.

  • Page 172

    ENV - Set Environment Master Starting Address #1 = 00000000 The base address of the VMEbus resource that is accessible from the local bus. (Default = $00000000, end of calculated local memory) Master Ending Address #1 = 1FFFFFFF? The ending address of the VMEbus resource that is accessible from the local bus.

  • Page 173

    CNFG and ENV Commands Master Starting Address #3 = 00000000? Base address of the VMEbus resource that is accessible from the local bus. (Default = $00000000) Master Ending Address #3 = 00000000? Ending address of the VMEbus resource that is accessible from the local bus.

  • Page 174

    ENV - Set Environment Master Address Translation Address #4 = 00000000? Enables the VMEbus address and the local address to differ. The value in this register is the base address of the VMEbus resource associated with the starting and ending address selection from the previous questions.

  • Page 175

    Specifies the base address ($FFFF00x0) in Short I/O for this board. (Default = $00) VMEbus Global Time Out Code = 02? Controls the VMEbus time-out interval when the MVME1603/ 1604 is system controller. (Default = $02, 256 microseconds) VMEbus Access Time Out Code = 02? This controls the local-bus-to-VMEbus access time-out interval.

  • Page 176

    ENV - Set Environment 6-20...

  • Page 177: Motorola Computer Group Documents

    Contacting your local Motorola sales office. Accessing the World Wide Web site http//: www.mcg.mot.com (listed on the back cover of this and other MCG manuals) and selecting “Product Literature”.

  • Page 178: Table A-1. Motorola Computer Group Documents

    MVME712M Transition Module and P2 Adapter Board User’s Manual MVME712M/D MVME760 Transition Module User’s Manual VME760A/UM SIM705 Serial Interface Module Installation Guide SIM705A/IH Note Motorola documents marked with a * in the above list can be purchased as a set under part number LK-V1600-1.

  • Page 179: Manufacturers' Documents

    To further assist your development effort, Motorola has collected some of the non-Motorola documents in this list from the suppliers. This bundle can be ordered as part number 68-PCIKIT.

  • Page 180

    Table A-2. Manufacturers’ Documents (Continued) Publication Document Title and Source Number PowerPC 604 RISC Microprocessor User’s Manual MPC604UM/AD Motorola Literature and Printing Distribution Services P.O. Box 20924 Phoenix, Arizona 85036-0924 Telephone: (602) 994-6561 FAX: (602) 994-6430 IBM Microelectronics MPR604UMU-01 Mail Stop A25/862-1...

  • Page 181

    Related Documentation Table A-2. Manufacturers’ Documents (Continued) Publication Document Title and Source Number Alpine VGA Family - CL-GD544X Technical Reference Manual 385439-004 Fourth Edition Cirrus Logic, Inc. (or nearest Sales Office) 3100 West Warren Avenue Fremont, California 94538-6423 Telephone: (510) 623-8300 FAX: (510) 226-2180 DECchip 21040 Ethernet LAN Controller for PCI EC-N0752-72...

  • Page 182

    Manufacturers’ Documents Table A-2. Manufacturers’ Documents (Continued) Publication Document Title and Source Number M48T18 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet M48T18 SGS-Thomson Microelectronics Group Marketing Headquarters (or nearest Sales Office) 1000 East Bell Road Phoenix, Arizona 85022 Telephone: (602) 867-6100 DS1643 Nonvolatile Timekeeping RAM Data Manual DS1643/ DS1643LPM...

  • Page 183

    Related Documentation Table A-2. Manufacturers’ Documents (Continued) Publication Document Title and Source Number Z8536 CIO Counter/Timer and Parallel I/O Unit DC-8319-00 Product Specification and User’s Manual ® (in Z8000 Family of Products Data Book) Zilog, Inc. 210 East Hacienda Ave., mail stop C1-0 Campbell, California 95008-6600 Telephone: (408) 370-8016 FAX: (408) 370-8056...

  • Page 184: Related Specifications

    Related Specifications Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.

  • Page 185

    Related Documentation Table A-3. Related Specifications (Continued) Publication Document Title and Source Number IEEE - PCI Mezzanine Card Specification (PMC) P1386.1 Draft 2.0 Institute of Electrical and Electronics Engineers, Inc. Publication and Sales Department 345 East 47th Street New York, New York 10017-21633 Telephone: 1-800-678-4333 IEEE Standard for Local Area Networks: Carrier Sense Multiple Access IEEE 802.3...

  • Page 186: Specifications

    Related Specifications Table A-3. Related Specifications (Continued) Publication Document Title and Source Number Peripheral Component Interconnect (PCI) Local Bus Specification, PCI Local Bus Revision 2.0 Specification PCI Special Interest Group P.O. Box 14070 Portland, Oregon 97214-4070 Marketing/Help Line Telephone: (503) 696-6111 Document/Specification Ordering Telephone: 1-800-433-5177or (503) 797-4207 FAX: (503) 234-6762...

  • Page 187: Cooling Requirements

    Specifications Specifications Table B-1 lists the general specifications for the MVME1600-001 and MVME1600-011 base boards. The subsequent sections detail cooling requirements and FCC compliance. A complete functional description of the MVME1600-001 and MVME1600-011 base boards appears in Chapter 2. Specifications for the mezzanine modules (processor/memory, DRAM, and optional PCI mezzanine) can be found in the documentation for those modules.

  • Page 188

    Cooling Requirements Cooling Requirements The Motorola MVME1603/1604 family of Single Board Computers is specified, designed, and tested to operate reliably with an incoming air temperature range from 0° to 55° C (32° to 131° F) with forced air cooling of the entire assembly (base board and modules) at a velocity typically achievable by using a 100 CFM axial fan.

  • Page 189: Emc Compliance

    Specifications EMC Compliance The MVME1603/MVME1604 Single Board Computer was tested in an EMC-compliant chassis and meets the requirements for EN55022 Class B equipment. Compliance was achieved under the following conditions: Shielded cables on all external I/O ports. Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel.

  • Page 190

    EMC Compliance...

  • Page 191

    MVME712M I/O makes port 3 async only. Asynchronous Serial Ports The MVME1603/MVME1604 uses a PC87303 ISASIO chip from National Semiconductor to implement the two asynchronous serial ports (in addition to the disk drive controller, parallel I/O, and keyboard/mouse...

  • Page 192: Synchronous Serial Ports

    The MVME1603/MVME1604 hardware supports asynchronous serial baud rates of 110B/s to 38.4KB/s. For detailed programming information, refer to the PCI and ISA bus discussions in the MVME1603/MVME1604 Single Board Computer Programmer’s Reference Guide and to the vendor documentation for the ISASIO device.

  • Page 193: Eia-232-d Connections

    Serial Interconnections EIA-232-D Connections The EIA-232-D standard defines the electrical and mechanical aspects of this serial interface. The interface employs unbalanced (single-ended) signaling and is generally used with DB25 connectors, although other connector styles (e.g., DB9 and RJ45) are sometimes used as well. Table C-2 lists the standard EIA-232-D interconnections.

  • Page 194: Interface Characteristics

    Interface Characteristics The EIA-232-D interface standard specifies all parameters for serial binary data interchange between DTE and DCE devices using unbalanced lines. EIA-232-D transmitter and receiver parameters applicable to the MVME1603/MVME1604 are listed in the following tables.

  • Page 195: Eia-530 Connections

    < +15V) 3000 7000 The MVME1603/MVME1604 conforms to EIA-232-D specifications. Note that although the EIA-232-D standard recommends the use of short interconnection cables not more than 50 feet (15m) in length, longer cables are permissible provided the total load capacitance measured at the interface point and including signal terminator does not exceed 2500pF.

  • Page 196: Table C-5. Mvme760 Eia-530 Interconnect Signals

    EIA-530 Connections asynchronous. It is adaptable to balanced (double-ended) as well as unbalanced (single-ended) signaling and offers the possibility of higher data rates than EIA-232-D with the same DB25 connector. Table C-2 lists the EIA-530 interconnections that are available at MVME760 serial ports 3 and 4 (J7 and J2 on the board surface, with port 4 also available as on the front panel) when those ports are...

  • Page 197

    Serial Interconnections Table C-5. MVME760 EIA-530 Interconnect Signals (Continued) Signal Signal Name and Description Number Mnemonic Data Terminal Ready (A). Output from DTE to DCE indicating that the DTE is ready DTR_A to send or receive data. Remote Loopback (A). Reroutes signal within remote DCE. In DTE configuration, RL_A always tied inactive and driven false.

  • Page 198

    Inversion of signals may be required (e.g., plus polarity MARK to minus polarity MARK may be achieved by inverting the cable pair). EIA-530 interface transmitter and receiver parameters applicable to the MVME1603/MVME1604 are listed in the following tables. Table C-6. EIA-530 Interface Transmitter Characteristics Value...

  • Page 199: Proper Grounding

    Serial Interconnections Table C-7. EIA-530 Interface Receiver Characteristics Value Parameter Unit Minimum Maximum ±12 Differential input voltage ±12 Input offset voltage Differential input high threshold voltage −200 Differential input low threshold voltage Input hysteresis Ω Input impedance (−15V < V <...

  • Page 200

    Proper Grounding C-10...

  • Page 201

    DTroubleshooting CPU Boards: Solving Startup Problems Introduction In the event of difficulty with your CPU board, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment.

  • Page 202

    Troubleshooting CPU Boards: Solving Startup Problems Table D-1. Basic Troubleshooting Steps for ALL CPU Boards (Continued) Condition Possible Problem Try This: II. There is a display A. The keyboard or Recheck the keyboard and/or mouse connections and power. on the terminal, mouse may be but input from the connected...

  • Page 203: Table D-2. Troubleshooting Mvme1603/mvme1604 Boards

    Introduction Table D-2. Troubleshooting MVME1603/MVME1604 Boards Condition Possible Problem Try This: III. Debug prompt A. Debugger 1. Disconnect all power from your system. EPROM/Flash PPC1-Bug> 2. Check that the proper debugger EPROM or debugger Flash does not appear may be missing memory is installed per this manual.

  • Page 204

    Troubleshooting CPU Boards: Solving Startup Problems Table D-2. Troubleshooting MVME1603/MVME1604 Boards (Continued) Condition Possible Problem Try This: 6. You may need to use the cnfg command (see your board Debugger Manual) to change clock speed and/or Ethernet Address, and then later return to: env <CR>...

  • Page 205: Abbreviations, Acronyms, And Terms To Know

    Glossary Abbreviations, Acronyms, and Terms to Know This glossary defines some of the abbreviations, acronyms, and key terms used in this document. See thick Ethernet. 10Base5 See thin Ethernet. 10Base2 See twisted-pair Ethernet. 10BaseT Asynchronous Communications Interface Adapter ACIA Advanced Interactive eXecutive (IBM version of UNIX) The main overall design in which each individual hardware architecture component of the computer system is interrelated.

  • Page 206

    Glossary Basic Input/Output System. The built-in program that BIOS controls the basic functions of communications between the processor and the I/O devices (peripherals). Also referred to as ROM BIOS. Bit Boundary BLock Transfer. A type of graphics drawing BitBLT routine that moves a rectangle of data from one area of display memory to another.

  • Page 207

    Glossary COder/DECoder CODEC The signals of (R-Y) and (B-Y) without the luminance (-Y) signal. Color Difference (CD) The Green signals (G-Y) can be extracted by these two signals. Composite Video Signal (CVS/CVBS) Signal that carries video picture information for color, brightness and synchronizing signals for both horizontal and vertical scans.

  • Page 208

    Glossary bit or 8-bit units that most systems use. With the transfer of larger bits of information, the machine is able to perform much faster than the standard ISA bus system. Enhanced Parallel Port Erasable Programmable Read-Only Memory. A memory storage EPROM device that can be written once (per erasure cycle) and read many times.

  • Page 209

    Glossary The term used to describe any of the physical embodiments of a hardware computer system, with emphasis on the electronic circuits (the computer) and electromechanical devices (peripherals) that make up the system. A computing system is normally spoken of as having two major components: hardware and software.

  • Page 210

    Musical Instrument Digital Interface. The standard format for MIDI recording, storing, and playing digital music. Multimedia Personal Computer The PowerPC-to-PCI bus bridge chip developed by Motorola for MPC105 the Ultra 603/Ultra 604 system board. It provides the necessary interface between the MPC603/MPC604 processor and the Boot ROM (secondary cache), the DRAM (system memory array), and the PCI bus.

  • Page 211

    Glossary The ability to record additional information, such as digitized multisession photographs, on a CD-ROM after a prior recording session has ended. A video system in which every pixel is refreshed during every non-interlaced vertical scan. A non-interlaced system is normally more expensive than an interlaced system of the same resolution, and is usually said to have a more pleasing appearance.

  • Page 212

    256-entry buffer and a 32KB unified (instruction and data) cache. It provides a 64-bit data bus and a separate 32-bit address bus. PowerPC 601 is used by Motorola, Inc. under license from IBM. The second implementation of the PowerPC family of PowerPC 603™...

  • Page 213

    PRP-compliant system using a PowerPC processor. PowerStack™ RISC PC (System Board) A PowerPC-based computer board platform developed by the Motorola Computer Group. It supports Microsoft’s Windows NT and IBM’s AIX operating systems. See PowerPC Reference Platform (PRP).

  • Page 214

    Glossary Small Computer Systems Interface. An industry-standard high- SCSI speed interface primarily used for secondary storage. The SCSI-1 implementation provides up to 5 Mbps data transfer. An improvement over plain SCSI; and includes command SCSI-2 (Fast/Wide) queuing. Fast SCSI provides 10 Mbps data transfer on an 8-bit bus.

  • Page 215

    Glossary Super Video Graphics Array (IBM). An improved VGA monitor SVGA standard that provides at least 256 simultaneous colors and a screen resolution of 800 x 600 pixels. One-way broadcast of digital information. The digital information Teletext is injected in the broadcast TV signal, VBI, or full field, The transmission medium could be satellite, microwave, cable, etc.

  • Page 216

    When data is copied from disk to main memory, the physical address is changed to the virtual address. See VESA Local bus (VL bus). VL bus MCG second generation VMEbus interface ASIC (Motorola) VMEchip2 MCG ASIC that interfaces between the PCI bus and the VME2PCI VMEchip2 device.

  • Page 217

    5-4 differences 1-1 firmware (PPCBug) 5-1, 6-1 layout 1-7, 1-18 decimal number 4 block diagram diagnostics 5-1 MVME1603/MVME1604 3-4 test groups 5-7 Board 3-16 disk drive configuration 1-6 connector 4-15 configuration register 3-16 controller 3-10, 3-12, C-1...

  • Page 218

    Index endian issues 2-25 53C825 or 53C810(SCSI) 2-28 general-purpose readable jumpers big-endian mode 2-26 MVME1600-001 base board 1-8, 1-23 GD5434 (graphics) 2-28 global bus timeout 1-45 little-endian mode 2-27 graphics (GD5434) 2-28 MPC105 function 2-25 graphics interface 3-8 PCI domain 2-28 ground connections C-9 processor/memory domain 2-25 VME2PCI function 2-28...

  • Page 219

    ROMboot enable 6-7, 6-11 values 3-26 ROMFAL 6-10 module ID (syn/async ports) 3-16 ROMFAL/ROMNAL values 3-26 multiplexing function (P2) 3-16, 3-18 ROMNAL 6-11 MVME1603/MVME1604 interrupt architecture 2-20 SCSI (53C825 or 53C810) 2-28 NETboot enable 6-8 bus 6-5 Network Auto Boot enable 6-8...

  • Page 220

    Index set environment to bug/operating system (ENV) 6-3 shielded cables (see also cables) B-2 Short I/O address decoder 6-18 slave address decoders 6-13 enable 6-14 sources of reset 2-24 speaker output 1-47, 3-14, 3-24 specifications, base board B-1 SYSFAIL* 6-5 system controller 1-38 reset (SRST) 3-19...

  • Page 221

    3/16” & 1/4” spine 86 - 100 pages ® ™ 5/16” spine 102 - 180 pages ® ™ 3/8” - 1/2” spine 182 - 308 pages MVME1603/MVME1604 Single Board Computer 5/8” - 1 1/8” spine Installation and Use 2 lines allowed...

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