Table 3-2. P2 Multiplexing Sequence - Motorola MVME1603 Installation And Use Manual

Block Diagram
3
3-18
Four signals are involved in the P2 multiplexing function: MXDO, MXDI,
MXCLK, and MXSYNC
MXDO is a time-multiplexed data output line from the main board and
MXDI is a time-multiplexed line from the MVME760 module. MXCLK
is a 10MHz bit clock for the MXDO and MXDI data lines. MXSYNC
asserted for one bit time at time slot 15 (refer to the following table) by the
MVME1600-001 base board. The MVME760 transition module uses
∗
MXSYNC to synchronize with the base board.
A 16-to-1 multiplexing scheme is used with MXCLK's 10MHz bit rate.
Sixteen time slots are defined and allocated as follows:

Table 3-2. P2 Multiplexing Sequence

MXDO (From Base Board)
Time Slot Signal Name
0 RTS3
1 DTR3
2 LLB3/MODSEL
3 RLB3
4 RTS4
5 DTR4
6 LLB4
7 RLB4
8 IDREQ
9 Reserved
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 Reserved
15 Reserved
∗
.
MXDI (From MVME760)
Time Slot
0
1
2
3
4
5
6
7
∗
8
9
10
11
12
13
14
15
∗
Signal Name
CTS3
DSR3/MID1
DCD3
TM3/MID0
RI3
CTS4
DSR4/MID3
DCD4
TM4/MID2
RI4
LANPWR
Reserved
Reserved
Reserved
Reserved
∗
GENIO_PRESENT
is